At IEDM 2014, IBM claims that for PCM, non-volatility/data-retention is no longer essential. Ron Neale takes a close look.
In its invited paper [Ref 1] at IEDM 2014, IBM offers a headline-grabbing position: For PCM, non-volatility/data-retention is no longer essential. It might cause many PCM developers, who for a long time have been struggling with the problem, to breathe a sigh of relief, albeit perhaps short lived in the light of what follows.
As always the devil is in the detail, and, in this case, it was for the application of PCM (phase change memory) to SCM (storage-class memory). SCM is defined as the location in a multi-processor memory hierarchy between the NAND-flash based solid state drives (SSDs) as the system memory and the SRAM closely linked to the processors. To date, because DRAM in its SCM role is about three orders of magnitude faster than Flash, it is able to deal with the frequent fetches from the system memory and now more often occupies this space.
The problem is the growth of processor parallelism while system memory latency is remaining roughly constant. The solution to the problem of servicing the multiple fetches from system memory is to add more DRAM. This increased cost of adding more DRAM in order to maintain bandwidth is imposing an unacceptable cost burden, so this could open an opportunity for PCM.
SCM essentials for PCM
The proposition in the paper is that for PCM in an SCM role, long-term non-volatility is not essential. However, what is essential is a long list, summarized in Figure 1, of essential developments including: a need to optimize the critical and performance limiting SET operation; low-power operation; high performance, write/erase endurance; high bit density per chip; scaling; and low cost. SCMs have low read to write ratios, so to reduce switching power dissipation between read and write operations, diodes as matrix selector devices will need to be replaced with vertical surround gate (VSG) MOSFETs, where it is claimed it should be possible to achieve a 6F2 cell size similar to that of a DRAM.
The list of essentials for PCM in its possible future SCM role (diagrammatic).
Equaling the DRAM is not enough, to reduce costs PCM must scale beyond DRAM and, to do that, multi-bit single cell operation beyond the two bits that has been demonstrated (although not yet commercially) will be essential. So, those two requirements must be added to the list of SCM performance essentials. In addition, it is now accepted that thermal crosstalk will be a problem below 20 nm, so another refinement that must be added to the SCM essentials list is thermal barriers. (Metal nitrides are suggested as a suitable thermal isolation barrier solution.)
To support claims that PCM write/erase lifetimes of 1010 cycles should be possible, the IBM paper points to write/erase lifetime or endurance data produced in 2003. This is data that ignores the fact that until 2013, the few PCM products that have reached the commercial market in each lithographic scaling step have produced a reduction in write/erase lifetime or endurance (from 1x106 at 90 nm to 1x105 cycles at 45 nm). The suggestion in the paper was wear leveling as a possible solution.
Optimizing SET time
Top of the list of essentials for any future PCM-SCMs is the need to optimize the performance-limiting SET operation, by reducing time and power. SET time is the longer of the two PCM write operations. The IBM paper will offer examples of three materials (A), (B), and (C) with (SET time nano-seconds/retention times in hours at 85 Celsius) of 3x102ns/106 hrs, 1.3x102 ns /2x105 hrs and 50ns/2x103 hrs, respectively. Clearly, if non-volatility is not a problem, then the material (C) would be the choice with only 2,000 hours of retention time at 85° Celsius.
Optimization of the SET time has two parts: finding the best material composition and pulse shaping. To explore the latter I extracted data from the ground-breaking piece of work by a team at IBM, Zurich, on crystal growth rate in PCM structures [Ref 2 & 3]. From which, for the first time, it is now possible to link in a continuum SET time, elevated data retention, and the effects of vertical scaling for one composition. Two example curves are shown in Figure 2 covering the temperature range from the melting to temperature to below 85°C for Ge2Sb2Te5. The curves shown are for a device with an inter-electrode spacing of 20 nm and a second similar device vertically scaled to 10 nm.
Clearly, optimization, by minimizing the SET time, will require pulse shaping and careful design of the SET pulse to maintain the temperature at the growing crystal interface close to that required for maximum crystal growth rate.
One possible problem might be related to the relatively small difference between the temperature for maximum crystal growth (750K) and the melting temperature of 877K. As illustrated in Figure 3, this would appear to require maintaining temperature up-gradient from the region of maximum crystal growth close to or at the melting temperature. This might require SET current values close to those required for reset with the addition of pulse shaping or profiling. At the moment, the impact of this on performance (i.e., write/erase endurance) and the power dissipation budget is unknown, but it is likely to be significant.
The SET sequence for optimum SET time.
In [Ref 2] IBM indicated that it had other PCM materials that offered crystal growth rates that are faster than the Ge2Sb2Te5 material used for the results of Figure 2, without any disclosure of the composition or now, in the light of the SCM application proposition, the temperature for maximum crystal growth and the activation energy in the data retention regime.
The SCM IBM paper at IEDM 2014 considers single effects and performance characteristics that might give credibility to the claims for an SCM future for PCM, but it seems to ignore the fact that many of these are interacting variables. To link the list of the SCM essential structural and electrical characteristics in a single device and then in a commercial memory array will be challenging, time consuming, and require a significant amount of research-and-development time and money. There is just the possibility that a ReRAM device will be able to fulfill the requirement.
The paper author's position keeps PCM dreams alive but, like the proverbial curate's egg, it was only good in parts, “Although PCM will not replace any incumbent memories, with the successful introduction of PCM-based SCM, TCAM and neuromorphic memory, PCM will transform the future semiconductor landscape.” (TCAM: Ternary Content Addressable Memory.)