2015 will likely be the year of widespread awareness and adoption of giga-scale SPICE. Willy Wonka may agree: "So much time and so little to do. Wait a minute. Strike that. Reverse it."
So much to do, so little time. This overworked expression could be etched into the doorway of every engineering organization. Though trite, what it conveys is far from trivial.
Certainly, this bit of dialogue from the 1971 movie Willy Wonka and the Chocolate Factory could apply to chip design. What designer hasn't stared at his or her computer screen, exasperated and thinking the same thing? Very few, I imagine.
The latest challenges coming at an overworked designer are those related to moving to advanced SoC or IP designs using leading-edge process technologies. They are forcing designers to look far more critically at their carefully constructed and formerly effective design flows. The trend in 2015 could be the start of a widespread retooling effort to stave off and wrestle these challenges.
SPICE and FastSPICE simulators are good examples of the intractable challenges. Circuit designers have relied on them for many years, but their limitations have become too onerous to ignore, particularly for the characterization and verification of large designs, such as embedded memory or a SoC's critical path. A string of tricky process variations, layout dependent effects (LDE), noise effects, and reduced supply voltage lead to smaller design margin and thus higher risk and tapeout costs. It's forcing designers to use more accurate timing, power, and noise models in their SoC designs and to perform more careful and accurate verifications across a wide range of variation and operating conditions.
It's a huge amount of simulation work. So much to do, so little time. As a result, designers want to make sure the time they spend on simulations is valuable. That is, simulations must be accurate first and foremost, then efficient.
Unfortunately, FastSPICE simulators, the choice for design characterization and verification for a long time, compromise accuracy in the range of 10-15% compared to golden SPICE. They do not offer sufficient accuracy, especially for the small currents that are critical for low-power design and achieving sufficient noise margins. FastSPICE simulations using special fine-tuned options based on often nonconverged DC further lower the user's confidence in the results. This means that, when designers rely on FastSPICE to generate timing or power models or to verify the functions or circuit before tapeout -- especially low-power applications sensitive to small current or noise elements -- they don't know when to trust the results. Design teams may end up running the risk of expensive respins and missing market windows. No one has time for that.
Furthernore, there's no golden signoff reference for FastSPICE. The traditional SPICE simulators used to be the "golden" to validate FastSPICE. However, none of the commercially available pure SPICE simulators can directly offer the simulation capacity of those advanced designs. With ongoing process technology advancement, despite the slowing of Moore's Law, circuit sizes continue to increase, and giga-scale designs are very common; i.e., circuit components may easily reach 100 million elements and even upwards of a billion-plus elements. Moving to 16 nm and beyond, 3D device structures add further capacity and accuracy challenges.
Times are changing. Design teams have been evaluating a new type of SPICE simulator known as giga-scale SPICE simulators, which are able to support giga-scale circuit simulation with a pure SPICE engine. They offer the combination of SPICE-level accuracy and FastSPICE-like capacity and performance. Giga-scale SPICE can be a golden reference for FastSPICE and a natural replacement for memory characterization, large block simulation, and full chip verification.
As a result, 2015 will likely be the year of widespread awareness and adoption of giga-scale SPICE. Willy Wonka may agree: "So much time and so little to do. Wait a minute. Strike that. Reverse it."
-- Dr. Bruce McGaughy is chief technology officer and senior vice president of engineering of ProPlus Design Solutions Inc. He was most recently the chief architect of the simulation division and distinguished engineer at Cadence Design Systems Inc. He previously also served as an R&D VP at BTA Technology Inc. and Celestry Design Technology Inc., and later an engineering group director at Cadence Design Systems. He holds a PhD in EECS from the University of California at Berkeley.