Embedded Systems Conference
Breaking News
Blog

IoT Feels Unintended Consequences

NO RATINGS
View Comments: Newest First | Oldest First | Threaded View
Page 1 / 2   >   >>
Steve_Casselman
User Rank
Author
Re: Real time performance and OpenCL Programming Model
Steve_Casselman   1/20/2015 2:28:49 PM
NO RATINGS
Altera's OpenCL BSP (board support package) can contain any HDL code including I/Os and real time controllers. The HDL blocks have ports that the complier knows about through a XML file. The compiler reads the HDL port description at compiler time and it knows the names to generate to connect to the HDL. We called these HDL ports to the real world "I/O
channels". You can then read/write to these I/O channels in real time.


Since you can have multiple concurrently running kernels one's kernel code can interface directly to the outside world. This is really useful when the I/O is an Ethernet UDP port talking directly to a stock trading floor or a WiFi connection to an emergency shutoff switch.

Steve_Casselman
User Rank
Author
Re: How to program FPGAs
Steve_Casselman   1/16/2015 2:54:05 PM
NO RATINGS
Altera did something visionary when they designed their OpenCL compiler. They decided to use the industry standard Clang front end parser. Why is this important? The output from Clang is LLVM (Low Level Virtual Machine). Just about every compiler you can think of can output LLVM. Altera wisely started an open standard called "The Standard Portable Intermediate Representation for Device Programs" of SPIR. See the Khronos website for more (interesting) details. SPIR will allow the Altera compiler to work with any high level language.

  OpenCL has a host/accelerator model. The Altera OpenCL compiler is masterful at pipelining programs. The SDK has a lot of great features like the emulator that allows you to run a high fidelity model of the FPGA on a CPU. This makes writing code for hardware as fast and simple as writing programs for software. Any pragmas used are about loop unrolling, nothing that any high performance programmer would do. You still have the long compile times when you do the final hardware compile. The compiler does a static analysis and tells you if the compiler can pipeline your code and exactly where the problems are. Most of my day is making sure customer programs/kernels are pipelined.

 Altera also has channels, which are kernel to kernel custom pipelines that allow each kernel to run concurrently. Channels also can hook directly to I/O signals which means you can talk directly to I/O form your kernel code. It's not all magic. You still have to do the board support package (BSP) in which you have to close timing and what not. BSP design is a regular HDL activity which includes timing closure for all infrastructure modules. While channels is an Altera OpenCL extension channels are too powerful and too easy to implement in a FPGA not to support such functionally.

 The best thing about the compiler is you never have worry about timing closure for the generated hardware. Generated hardware uses a single clock. The compiler looks into the timing report and sees what frequency the hardware can run at.  The runtime then sets a reconfigurable PLL to the frequency that the hardware can best run at. I worked with the compiler for 9 months before I opened the normal hardware design tools.

 Altera's OpenCL SDK is a relatively mature programming environment. The compiler does a static analysis that tells you if your code is pipelined. There is an emulator so you can run and debug your kernel code without doing a simulation or writing test benches. There is real profiler that you compile into the hardware that gives you the real data bandwidth of all memory and channel data movement by inserting hardware counters. Altera has a run time environment that takes care of reconfiguration, moving data from the host to the accelerator and back, telling the hardware where the transferred data is and other functions that it takes to have a complete hardware accelerated application run.

Matthieu Wipliez
User Rank
Author
Re: How to program FPGAs
Matthieu Wipliez   1/12/2015 12:30:48 PM
NO RATINGS
When you say that Verilog "fits that description", are you saying that Verilog too uses a syntax similar to C? Sure arithmetic operators are the same and "if" is supported in both languages, but that's about it. Here is a "while" loop in C (say "count" is volatile and this executes at one iteration per cycle):
while (count != 8) {
  count++;
}
// blah

Well, here is the equivalent code in Verilog:
always @(negedge reset_n or posedge clock) begin
  if (~reset_n) begin
    count <= 4'b0;
    FSM <= init;
  end else begin
    case (FSM)
      init: begin
        if (count != 4'h8) begin
          count <= count + 1;
          FSM <= init;
        end else
          FSM <= next_state;
      end

      next_state: // blah
    end
  end
end

I don't really see the resemblance, in fact it is nothing like C. I mean even the "begin"/"end" are reminding me more of Pascal than C. Not to mention that like with any HDL there can't really be any structure because every synchronous piece of code is just laid out as a gigantic switch case in the always block (process in VHDL). Or worse in two blocks (one combinational and one sequential) which helps a lot... in obfuscating the code. Or even worse, multiple always blocks to make it as low-level as possible (sacrificing readability on the altar of "performance" but of course without measuring if there's even the slightest difference).

Sorry. Back to your question :-) Cx has arrays that are always implemented as register-based arrays, but if you want to use RAM memory currently you must instantiate one of the built-in inferred RAM entities. We have planned to make it possible for the user to tell the compiler to implement arrays as RAM for convenience (but of course it will still be possible for users to instantiate their RAM manually).

KarlS01
User Rank
Author
Re: How to program FPGAs
KarlS01   1/12/2015 11:49:59 AM
NO RATINGS
@Matthieu:  I think Verilog also fits that description, else you have a round about way of writing Verilog.  Others have simply implemented the appropriate C subset.  Pointers are memory addresses -- how does Cx address memory?

Matthieu Wipliez
User Rank
Author
Re: How to program FPGAs
Matthieu Wipliez   1/12/2015 10:58:35 AM
NO RATINGS
@KarlS01 we've been working on Cx for 3 years so it's still "new" I'd say, and it is certainly more recent than VHDL/Verilog. We've gone through many iterations during that tim, we've even changed the name of the language to make it easier to search for, it was previously called "C~".

Cx is not an extension of C. It's a programming language of its own for hardware design that uses a syntax similar to C (though simpler and more regular). It is fully synthesizable and we generate both Verilog and VHDL.

There are many reasons why we created a new language. C is good for software, but half of its semantics make no sense for hardware. No bit-accurate types? Pointers? Memory allocation? And it has no parallelism (except for C11 threads, but still that's pretty limited).

KarlS01
User Rank
Author
Re: How to program FPGAs
KarlS01   1/12/2015 10:25:46 AM
NO RATINGS
@Matthieu:"I've learned just enough of VHDL and Verilog so I can read existing code, and more importantly understand how to generate code in these languages automatically"

1) Cx is a new language("it takes years to create a new language")

2) Cx is an extension of C?

3) Do you generate HDL code for the plain old C part?  Or just Cx part?

KarlS01
User Rank
Author
Real time performance and OpenCL Programming Model
KarlS01   1/12/2015 9:56:27 AM
NO RATINGS
"Trends in data acceleration and network enrichment -- both favorable to FPGAs -- are addressing needs for faster and predictable real-time performance, low-power WiFi, and Ethernet connections, and rapidly evolving device security."

OpenCL creates independent units of work and ships it off for processing.  Two kay points are indeppendence and customized processing.  Real time control can be similar because the sensors and control are independently processed.

Real time response needs custom processing just as OpenCL and accelerators do.

For many years mainframe computers had control units(custom) attach by channels to the cpu and memory.  An IOT hub is a miniature version of that. 



Looks like an opportunity for a general purpose controller with a customizable external interface(or even an existing general purpose in terface?).

Matthieu Wipliez
User Rank
Author
Re: How to program FPGAs
Matthieu Wipliez   1/12/2015 5:46:06 AM
NO RATINGS
@krisi you know what they say about standards? http://xkcd.com/927/ ;-)

Standards are a good thing for interoperability, and some standards (or de facto standards) are incredibly useful, things like TCP/IP are now ubiquitous. Standard does not necessarily mean "fixed", and in that particular case how TCP is used in practice has evolved to match today's requirements.

However, there are other "standards" that suffer from the design-by-committe effect, in which nobody is willing to make compromise and everybody is trying to add their own little feature. SystemVerilog would be a good example of that. And it's not the only one, on SemiWiki simguru was giving a testimony of how he "usually gets stomped on at EDA language committees" regarding mixed-signal design/simulation issues.

The key issue is to know when a standard is appropriate, and when it is not. For instance, C is awesome for many things, and the fact that it has been one of the most used programming languages of all time for so long is a testimony to that. It was standardized for the first time in 1989. But the fact that it's a (very) well-established standard should not be enough to decide it's the right choice for hardware, because as it turns out C is a really bad starting point for hardware design.

And the best is that typically EDA vendors take a standard but implement/extend them in a proprietary way! The "C" that Xilinx Vivado HLS claims to support is full of proprietary #pragma directives, and well-defined C semantics such as accessing memory with a pointer are magically transformed into accessing ports, or in other cases are just forbidden. And what about SystemC? Well you can write just about anything, since that's just C++. But then if you want to synthesize, you have to use a restricted, half-standardized subset of it. Which is then extended by proprietary #pragma and macros from one vendor, incompatible with the next vendor's toolchain.

@krisi @alex_m1 as I said in my previous comment, it's not so much about lifespan as it is about usefulness and being appropriate. Verilog and VHDL were appropriate at the time, in a world where chips were not so big and it was mostly about ASICs done by highly specialized experts.

Except the world has changed. Languages that require years of training to be proficient in are no longer appropriate, especially for systems engineers who need to know about electrical design and embedded software too. It's the main obstacle barring FPGAs from the mainstream, making maintenance a nightmare, preventing most end-users from doing any customization.

@alex_m1 it depends on your team, your language, your target (hardware is, well, hard), if you know where you're going, etc. Unless you're doing a small DSL targeting an existing environment (like on top of Ruby, or using the JVM), creating a new language still takes years.

@krisi to be honest I hate SystemC, I find it verbose and it feels clunky. I've learned just enough of VHDL and Verilog so I can read existing code, and more importantly understand how to generate code in these languages automatically :-) Why spend years getting to an expert level in Verilog when you could have a sufficient knowledge of Cx in days? And why would I want to spend weeks designing a piece of hardware that I can design in days?

alex_m1
User Rank
Author
Re: How to program FPGAs
alex_m1   1/9/2015 4:01:30 PM
NO RATINGS
Maybe even every 3 years is good ,i don't think with today's software tools it takes so long to perfect a language - i wonder what mathew, who implemented a language thinks about that.

But 5 years works too.

 

But AFAIK , verilog and vhdl still rule, and are at their base - very old languages. Even systmC is quite old.

krisi
User Rank
Author
Re: How to program FPGAs
krisi   1/9/2015 3:03:22 PM
NO RATINGS
Once every 5-10 years when things really change...not on annual basis...these are very complex harwdare languages and it takes several years to perfect them

Page 1 / 2   >   >>
March 2015 Cartoon Caption Contest: Mountain Climbing
March 2015 Cartoon Caption Contest: Mountain Climbing
The mountain had formed millions of years before when two tektronix plates collided.
208 comments
Flash Poll
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Top Comments of the Week