Performing ASIC-to-FPGA clock tree conversions by hand is difficult and time-consuming for designers; the use of automated gated clock conversion makes this task much less challenging.
As electronic companies design today's leading-edge ASICs, increasing costs and shortening development schedules are requiring ASIC designers to develop an early prototype. Prototypes are used to help accelerate hardware and software schedules and complete system verification. Companies often fulfill their prototyping requirements with platforms based on FPGAs, which provide developers the opportunity to have a hardware platform early in the design cycle.
Using a prototyping platform for initial software development has become standard practice that allows for faster software development and debug. Development work can be compiled and debugged on real hardware allowing needed bug fixes to be integrated early in the development cycle. In addition, the verification teams can utilize the prototyping platform to accelerate verification by allowing the testing of designs on FPGA hardware platforms very early in the process, thereby gaining a significant advantage in advance of final silicon becoming available.
All of this leads to the fact that many ASIC teams are tasked with creating an FPGA-based prototype to enable hardware-based debug, test, and early software development. In most cases, the design team provides nightly or weekly builds of the most current prototype to the software development and verification teams. These ongoing changes to the ASIC design mean that the hardware designers require some method of generating corresponding updates to the prototyping platform.
FPGA synthesis tools like Synplify Premier help automate the conversion of the ASIC design into its FPGA equivalent by directly reading the ASIC design files, including DesignWare IP blocks, ASIC RTL, constraints, and Verilog files. In addition, the tools provide an easy path to implement "FPGA friendly" designs by utilizing side files that specify which circuitry to remove, stub out, or substitute, and to automatically convert ASIC clock architectures into equivalent FPGA clocking structures.
Figure 1. Direct support of golden ASIC files and conversion side files.
By using the ASIC source files directly, designers can update and patch the main ASIC code without having to struggle with the conversion into a FPGA prototype. This helps eliminate duplicate code bases and synchronization issues through the direct import of the "golden" set of ASIC source files, such as RTL (including Verilog, VHDL, and SystemVerilog).
One area of particular note is the inherent complex clocking circuitry that often includes a large number of gated and internally generated clocks in an ASIC design. The Synopsys FPGA synthesis tools provide designers with an ability to address these complex clocking schemes by providing a path for automated gated clock conversion. It is not always necessary to convert all clocks from an ASIC design, but fitting the design into the FPGA device and meeting timing objectives are the ultimate goals.
There are some common situations that require unconverted clock structures to be modified, such as a large number of loads resulting in congestion issues or a large clock skew causing a failure to meet timing. Performing such a conversion by hand is difficult and time-consuming for designers -- the use of automated gated clock conversion makes this task much less challenging.
In ASICs, gated clocks generally serve to save power or to minimize the impact of clock glitches. In the example shown below, the gated clock includes a signal that "opens the gate," thereby allowing clock signals to propagate. Many types of structures -- such as AND, NAND, OR, NOR, XOR, and MUX -- may be used to implement the clock gating.
Figure 2. ASIC gated clock to FPGA converted clock.
As illustrated in this example, the tools will automatically convert an AND, OR, NAND or XOR-based ASIC gated clock into an FPGA converted clock by moving generated clock and gated clock logic from the clock pin of a sequential element such as a flip flop to the enable pin.
There are many types of gated ASIC clocks that need to be converted, including logic-based, latch-based, and generated clocks. Synplify automatically handles the various types of clocks for designers, thereby easing the task of developing and maintaining an FPGA-based prototyping platform.
Joe Mallett is a senior product marketing manager for FPGA-based synthesis software tools at Synopsys. He has 20 years of experience in design and implementation within the semiconductor and EDA industries. Before joining Synopsys, Joe was a senior product marketing manager at Xilinx Semiconductor where he worked to define and launch FPGA products. His background includes SoC design/prototyping, embedded software, HDL Synthesis, IP, and Product/Segment Marketing. He holds a BSEE from Portland State University.