Although traditional dimensional scaling looks ever darker, the emerging monolithic 3D technology is poised to bring back the light.
The term "dark silicon" refers to those portions of a device that need to be shut down in order to avoid overheating. In a recent IEDM 2014 short course by ARM's principal engineer, Greg Yeric, dark silicon was projected to account for "about one-third of total area in the 20nm technology node (including 16/14nm FinFETs), increasing to as much as 80% by the 5nm node," as reported by a recent Darker Silicon blog. Unlike the time that dimensional scaling could follow Dennard's Law, it is now getting harder to thin the gate dielectric without causing extreme rise in device leakage, and "as a result, while feature sizes have continued to shrink, threshold voltage has not." The following chart is from a DAC 2013 paper titled The EDA Challenges in the Dark Silicon Era:
This dark outlook seems even darker once the cost of this silicon is taken into account. At the last SEMI Industry Strategy Symposium (ISS), as reported in a blog titled Exponentially Rising Costs Will Bring Changes, Scott McGregor, President and CEO of Broadcom, presented the following charts:
This paints a very dark future for the industry. We would need to invest exponentially more in order to develop designs that use more expensive transistors, of which we would need to keep dark an increasing proportion. It seems that the Broadcom CEO's conclusion -- "major changes for the semiconductor industry moving forward" -- is unavoidable.
Looking for the light at the end of the tunnel, we can turn to ARM's CTO, Mike Muller, in a Cadence blog titled ARM Keynote: Will 'Dark Silicon' Derail The Mobile Internet? When he said "So how to light things up?" Muller started with three suggestions as follows:
- Push forward on new silicon technologies such as silicon-on-insulator (SOI).
- Use energy-efficient, high-density memories to fill some of the "dark" space.
- Combine the best process technologies to fulfill various functions with 3D ICs, which will "become a critical part of how we deliver power-efficient solutions."
Indeed, just this week it was reported in EE Times that Sony Joins FDSOI Club, which included a comment that "Sony was able to cut power consumption in its GNSS chip from 10mW to 1mW."
And at IEDM 2014 we could see multiple papers on monolithic 3D technologies and memories such as RRAM being formed as part of the back-end-of-line (BEOL) on top of the logic, effectively forming monolithic 3D circuits. It should be pointed out that -- in the general case of monolithic 3D -- the upper transistor layers are naturally SOI, so achieving increased power efficiency by combining the SOI reduction of transistor threshold while reducing the average interconnect length further reduces interconnect power and delay. CEA Leti had a workshop presenting their momentum on monolithic 3D through collaboration with ST Micro and IBM, and supported by Qualcomm, titled CoolCube, a powerful approach for further 3D VLSI scaling. The following chart from Leti presentation illustrates the monolithic 3D build up of worldwide ecosystem:
And the monolithic 3D light grows even brighter. Until recently, the path to monolithic 3D required change to the front-end-of-line (FEOL) process. An FEOL process change is always part of dimensional scaling, but it is expensive and -- in most cases -- undertaken only by the leading edge companies. Now, as was presented at the recent IEEE S3S 2014 conference, the emerging precise bonders -- e.g., from EVG or Nikon -- enable a Game Changer for Monolithic 3D; i.e., "…true monolithic 3D IC without the need for a new recipe for transistor formation. The process could be adapted by any current fab providing very competitive costs for a range of product enhancements and offer a long term road map for better offerings by scaling up."
The end result is that, although traditional dimensional scaling looks ever darker, the emerging monolithic 3D technology is poised to bring back the light.
PS A good conference to learn about emerging technologies, such as the IEEE SOI-3D-Subthreshold (IEEE S3S) 2015 conference, which will be held October 5th through 8th, 2015, in Sonoma, California.