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Intel Calls for 3D IC

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msporer
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Re: Double Patterning
msporer   3/9/2015 12:04:20 PM
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Yes, over time 28nm will continue to be with us as the cost effective node and the advanced nodes will continue to progress.  The gap between 28nm and what's next will grow.  I think we agree.

IJD
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Re: Double Patterning
IJD   3/9/2015 11:56:38 AM
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The cost of double (or multiple) patterning isn't a step function, it depends on how many layers you use it for (together with how many masks per layer) compared to the resulting chip area decrease and what happens to yield.

For example, the 20nm/16nm/14nm processes typically need double-patterning for 2 or 3 BEOL metal layers (+ vias), 1 or 2 MEOL layers, and 1 or 2 FEOL layers (depending on exact process choice) -- so on this alone there could be up to 2x variation in the number of masks depending on whether density or cost is the priority -- and I think Intel have 8 DP metal layers in 14nm so they've really prioritised density over cost!

Go to 10nm and the double-patterned layers may move to triple-patterning, and a lot of the single-patterned layers move to double -- the step up in mask count can easily be a lot bigger then going from 28nm to 20nm, and the density increase may be smaller depending on what limits it (e.g. whether SAC are used).

So it's easy to spend a lot on multiple patterning (what happened with the first sub-20nm FinFET processes) to get the "best" density, when by choosing a small decrease in density the cost reduction can be significant -- the key is to get the right tradeoff for the target market.

Either way it's clear that going beyond 28nm the chip cost saving per node is much smaller or negative, depending on when you measure it and what process choices are made, and whether you compare processes from one foundry or the open market price.

When you also allow for the fact that low-cost foundries liike SMIC will also come in to 28nm in a big way and not jump to DP for some time, it's clear that the market price of 28nm chips will be cheaper than DP nodes for at least the next few years.

Or_Bach
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what is this "monolithic 3D" - if it is not TSV?
Or_Bach   3/7/2015 8:31:58 PM
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The difference is 1:100,000 !

TSV is thicker than 50 micron wafer with over 5 micron via and keep-out zone.

Monolithic 3D is about 100nm layer with about 50nm via.

This represnt completly different utilty and costs.

While TSV is the "solution of the last resort", monolithic 3D should and already becoming the first resort path for future scaling.

sranje
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Re: 3D-IC and 450 mm
sranje   3/7/2015 4:53:17 PM
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Thank you Zvi for your persistence.

 

Recently there have been inputs on change of heart - toward 450mm once again. Clearly the foundry landscape has profoundly changed - never before TSMC lost the race to the next node...

 

I must admit --- in the end just what is this "monolithic 3D" - if it is not TSV?

msporer
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Double Patterning
msporer   3/6/2015 12:25:25 PM
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Double patterning is a step function increase in cost and capability.  Once you convert to DP you are going to continue to drive litho until that runs out of steam. So seems to me that DP@14nm or smaller will have the advantage over DP@22nm.

resistion
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Re: 3D NAND
resistion   3/6/2015 5:03:13 AM
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Many good points, but that last point with the big bucks on the cost graph by Samsung looks like V-NAND.

AKH0
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3D NAND
AKH0   3/5/2015 5:54:31 PM
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Although the experince with 3D NAND is not quite applicable to logic, there are a few lessons to learn:

1) 3D NAND - at least what is out there - is using a poly-Si channel which is far infrior to single crystal Si. There is even no room for laser crystallization to get a reasonable poly.

2) In the first generation, Samsung used a single patterning for BL metal as opposed to double pattering in 2D. This resulted in less BL capacitance. Allowing the BL to be roughly twice as long as what is used in state-of-the-art 2D NAND (~10mm as opposed to ~5mm). 

3) Overal, the transition from 2D to 3D (first generation), led to about 2X increase in programming speed, ~2X increase in memory density, and ~ 2X reduction in area overhead coming from pheriphery circuits (which do not scale well with technology).

 

 

Zeev00
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Re: 3D-IC and 450 mm
Zeev00   3/5/2015 5:41:03 PM
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Max Bohr (Intel) argues that "Wafers are more complex and expensive in the 14nm process which requires double patterning and thus more masks. However, greater gains in density mean overall cost per transistor continued to decline at 14nm, something Intel expects to continue for the next two nodes." Perhaps true, but seems like one could get similar or bigger cost reductions much easier at 22 nm through process & device optimization and monolithic 3D.

Or_Bach
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Re: 3D-IC and 450 mm
Or_Bach   3/5/2015 1:46:26 PM
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There are no missing pieces in the ecosystem, other the guts needed in adapting new technology path.

It is hard to guess which node would be the first. 28nm is the one that would make the best sense as it is the loest cost node and desrve the largest investment for upgade etc. But older nodes are more accessable and require lower investment.

The first application is already 3D NAND (predicting the past is easier ;-), to be follwed by image sensors as presented above: The next market segment adopting monolithic 3D scaling is the image sensors as recently reported by EE Times: CMOS Image Sensors Surpassing Moore's Law. Quoting: "imaging chips is downsizing the chip while simultaneously packing more pixels per unit size, thus one-upping processors and memory ... The CMOS imaging industry may make the 3-D TSV obsolete – before the processor and memory industry has even widely adopted it – by perfecting a wafer bonding technique that allows the connection between layers to be made with copper-to-copper (Cu-to-Cu) interconnects nearly as small as regular vias."

Doug_S
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$7400/wafer is inaccurate
Doug_S   3/5/2015 1:37:47 PM
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If it is part of an expansion, the process itself is only part of the cost.  The cost of putting up a new building and equipping it to house a fab costs billions on its own.  The delta between building that same expansion for 10nm versus 16nm or whatever is what matters.  That will be nowhere near $15.9 billion.

 

Also, a two year depreciation cycle is ludicruous.  TSMC uses processes for years, so a 10 year cycle is probably more appropriate, though obviously most of the depreciation would occur early when it is the leading edge process.  They still have decade old 90nm fabs running high volumes, still making money for them.

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