Moore's Law is not ending soon, yet it is not going to be the simple brute-force x0.7 dimensional scaling that dominated the industry for the last 5 decades.
In his famous 1965 paper Cramming more components onto integrated circuits, Moore wrote: “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year”. Dimensional scaling below 28nm will only increase the ‘component cost’ as described in 28nm – The Last Node of Moore's Law. While there is still a strong effort behind dimensional scaling to 14, 10 and 7nm – and possibly even beyond, a new scaling effort is emerging attempting to reduce the ‘component costs’ and increase integration by the other factors presented by Moore in his 1975 famous IEDM paper “Progress in digital integrated electronics." In the 1975 paper Moore updated the time scaling rate to every two years and suggested the following factors–see the following figure taken from his paper—helping to drive scaling forward:
- “Die size”—“larger chip area”
- “Dimension”—“higher density” and “finer geometries”
- “Device and circuit cleverness”
A fourth factor should have been added to the list above – improvement in manufacturing efficiency, which ensued from the increase in wafer sizes from 4” to 5” and all the way to the 12” of today.
In the past, all of these factors were aggregated into dimensional scaling as old fabs got obsolete and improvements predominantly were implemented in the new emerging node. Nowadays, as dimensional scaling has reached its diminishing returns phase, we can see a very diverse adaption of technology improvements.
In his keynote presentation at the 2014 Synopsys user group meeting, Art De Geus, Synopsys CEO, presented multiple slides to illustrate the value of Synopsys’ newer tools to improve older node design effectiveness. The following is one of them:
The following slide was taken from AMD’s President & CEO Dr. Lisa Su presentation in 2015 Semicon China, illustrating AMD’s improvements within the same 28nm technology node: