The EDA community faces multiple challenges at the 10nm and 5nm nodes that experts will discuss at Semicon West.
The timing of insertion for extreme ultraviolet lithography has been debated and discussed for a number of years. Some experts have expressed the belief that EUVL will be ready for high-volume manufacturing (HVM) in the 2020 timeframe.
Development work for the 10nm node has been done primarily using 193 immersion (multi-patterning) lithography, raising the question of whether designs will be backward compatible should EUVL become available. Juan Rey, senior director of engineering at Mentor Graphics, will attempt to answer that question at Semicon West 2015 (July 14-16) in San Francisco, Calif.
“If EUV becomes production ready in 2020, then it will be too late for the initial 10nm production tape outs,” said Rey.
“As such, for 10nm, EUV will have to show it is a cost-effective alternative to the most critical layers that currently require several multi-patterning (MP) exposures for immersion,” he said. “The cost comparison should consider both production costs and the adoption costs due to re-design and new masks,” he added.
Rey does not think it is possible at this time to come to a firm conclusion as to the feasibility of complete backwards compatibility.
“However, multi-patterning brings very specific requirements on designs that may not be required if EUV supplants MP for all the critical layers,” Rey said. “If that is the case, current design restrictions would represent a superset, and one could attain better fidelity, and possibly better performance by using EUV,” he added.
Rey explained that because the critical MP layers are primarily in the arena of standard cells and custom IP/design, the industry could expect that these layers are the best candidates for mid-course EUV adoption. “However, we have seen that every exposure technique brings its own restrictions on the design process, which cannot be discounted,” he said.
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