Using a feature-rich implementation tool helps designers focus on their own product differentiation while accelerating time to market and meeting cost targets.
The size and complexity of FPGAs is growing, but schedules are not. Designers continue to face tight deadlines and budgets, making it critical to find ways to improve productivity during product development. Synthesis runtimes range from several hours to an entire day for the largest and most complex designs. Therefore, designers need a set of tools that provides the best runtimes while not compromising area, timing, and quality of results (QoR).
A robust synthesis tool, such as Synplify Premier, offers designers with several technologies and methodologies to gain the best balance of runtime and QoR. In a normal design flow, getting to first hardware is critical to enable early system software development and system validation. Support for fast synthesis mode enables designers to gain a fast first time through the flow by trading off QoR. This provides a hardware platform that while may not be running at full performance can be utilized to quickly enable early system driver and software development in addition to earlier system validation, yielding a faster time to market.
Figure 1. Faster time to market with fast time to first hardware and incremental compiles coupled with RTL based debug.
Once the first working hardware platform is delivered, designers can start optimizing their design for best area vs. timing, which can require multiple iterations. There are several methodologies to address this requirement which encompasses both incremental design and multi-processing.
Figure 2. Multiple processing with automatic compile points accelerating runtimes.
Synplify Premier supports multiprocessing technologies, like Automatic Compile Points (ACP), which enables automatic partitioning of an FPGA design to enable parallel synthesis of large designs automatically leveraging multi-processor systems. Within a typical design, Synplify Premier automatically accelerates runtime and reduces manually defining design partitions and constraints by defining multiple compile points. In addition, accelerating subsequent synthesis runs is completed through incremental design by only recompiling the changed partitions. Combining fast synthesis mode and ACP with multiprocessing can provide designers with a 10X acceleration of runtimes.
In addition to ACP with multi-processing and fast synthesis, designers are able to automatically distribute synthesis runs across multiple machines enabling the best utilization of compute resources.
Figure 3. Synplify synthesis support for multi-machine and -processing accelerates runtimes.
All of these technologies combined provide designers with a fully scalable design while automating the overall process to dramatically increase productivity through the reduction of FPGA runtimes.
The landscape of FPGAs is evolving due to advancements in low power, high performance, and lower cost. Designs implement using these powerful FPGAs need tools and methodologies that deliver automation, faster turnaround times, and the fastest runtimes. Using a feature-rich implementation tool helps designers focus on their own product differentiation while accelerating time to market and meeting cost targets.
Joe Mallett is a senior product marketing manager for FPGA-based synthesis software tools at Synopsys. He has 20 years of experience in design and implementation within the semiconductor and EDA industries. Before joining Synopsys, Joe was a senior product marketing manager at Xilinx Semiconductor where he worked to define and launch FPGA products. His background includes SoC design/prototyping, embedded software, HDL Synthesis, IP, and Product/Segment Marketing. He holds a BSEE from Portland State University.
— Max Maxfield, Editor of All Things Fun & Interesting
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