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Semicon West: The Roadmap is 3D IC

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mendicant98
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M3D, ICs, IBM, GF, and IoT
mendicant98   7/27/2015 3:07:19 PM
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Two years ago, one view within Intel was that IC performance improvements based on planar technology ran out at the 10nm node, and cost improvements ran out at the 14nm node. Today, that view has moved downward: performance still improves down to 7nm, but cost improvements end at 10nm. But, this change in view has only come at great R&D cost. And, few companies can afford this cost in the future: Intel, Samsung, probably GF, maybe TSMC.

Cea-LETI at Semicon West showed a figure documenting the performance for a particular ITRS node, vs. the number of M3D layers executed with that level of technology. The result was dramatic: a 14nm node with two M3D layers out-performs a 10nm node fully-planar technology. Cost, however, was not folded into that analysis, and remains to be demonstrated (Zvi's last figure addresses the cost aspect of M3D). The implication, however, is that adding an M3D layer at one node, is less expensive than deploying the next-generation node of planar technology.

The merger of IBM Microelectronics and GF will likely result in application of M3D technology to nodes substantially larger than 14nm, especially for RF-SOI applications.

Finally, M3D technology advances more than just IC technology. IoT has not only entered the corporate consciousness (*every* major company has an IoT enterprise group or division), but also public and consumer consciousness. The ubiquitous nature of smartphones invites MEMS and sensors to be incorporated, beyond the GPS, gyro, and accelerometer sensors which they already contain. 

We are just scratching the surface. M3D technology will prove to be more than IC technology, well beyond more than Moore.

beinglass
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Monolithic 3D
beinglass   7/23/2015 6:18:30 PM
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Looks like even people were trying to avoid any monolithic 3D process development in the past, looks like there is no way out of it. Many reasons for that but the main issue is economic. Moore's law is teaching us that doubling the number of transistors on the chips within 18 (24) month is not a target by itself, the economic has to work by reduction of the price per transistor otherwise we are on a wrong path.

Looks like with the new technology nodes of < 20nm we are getting into unchartered water where the price per transistor starts to increase unlike in the past.

The only solution as the article portray is going 3D, so looks like we are starting a paradigm shift toward the unavoidable monolithic 3D.

3D Guy
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Yes, the roadmap is 3D IC
3D Guy   7/22/2015 11:57:39 PM
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Yes, Zvi, I think the industry consensus is that monolithic 3D will follow feature size scaling. Intel recently quoted savings of $1B by going to 10nm 2.5 years after 14nm (vs. their standard 2 year cadence). In the future, I expect to see the 2.5 years changing to 3 years and eventually to 4. Ultimately, people will need to explore monolithic 3D structures to complement feature size reduction.

bec0
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3DIC is indeed here
bec0   7/22/2015 8:23:49 PM
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Agreed Zvi! 3DIC has arrived, and except for a few applications, a monolithic style is what is required to move the industry forward. As even Mark Bohr has come to realize, we need vertical connectivity to be close to the horizontal connectivity that the industry has enjoyed for the last 50 years for 3DIC to make any impact. It's also good to see the recent words by Global Foundry's Jha, where he notes that only a few need pursue speed scaling (obstensively via dimensional scaling) and the majority of the industry needs to keep on delivering cost per function or cost per feature reductions.

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