With both Intel and Micron "keeping mum" on how they solved the 3D XPoint memory problem without using phase change memory, Ron Neale put on his inventor's hat and offered some further speculation.
There was an interesting answer to a question at Intel and Micron’s recent 3D XPoint memory announcement: “It does not use electrons. It’s a material property."
I assumed the speaker meant to say it does not store electrons like a NAND memory, so I asked Intel to clarify this point, but it had nothing further to say. Could the responder have actually meant to say it stores data like NAND as a structural effect and relies on a structural depletion effects?
Such an interpretation requires the speculative proposal of a possible memory mechanism. I call it the “egg yolk" model and named it the nano-particle depletion RAM (NpdRAM). While there might be many possible implementations, Figure 1 illustrates two.
In operation, starting with the left hand side of Figure 1, we have conducting or non-conducting nano-particles in a matrix of conducting material between two planar electrodes. The read current is able to pass between the nano-particles, or even through and between them. For a preferred implementation, the current paths are shown in green.
To write the memory, a higher current or voltage pulse is used which by thermal, chemical reaction, electro-chemical or electro-migration effects cause a non-conducting surface layer to form on the nano-particles. The formation of this layer depletes the inter-particle matrix material of one component, reducing its electrical conductivity. The two effects combined result in the high resistance memory state. This is shown in the upper left of figure 1, with the inter-particle detail on the far right. Red lines in figure 1 are used to indicate blocked current flow. In the rosy world of speculation, we do not have to specify the fine detail of the mechanism, only the concept.
The lower sequence in figure 1 shows a possible model where the high resistance surface coating is formed only on the leading edge of the nano-particles. Once again, the combined effect of the barrier and inter-particle element depletion required to create the barrier results in a high resistance bulk material and the high resistance state of the memory. In this case, for example, the nano-particles could be a something like a tantalum/titanium or tantalum/titanium oxide nano-particle in a matrix of an oxide of manganese compound. The result would be nano-particle rectifier junctions floating in a non-conducting matrix.
Depending on the particular mechanism, a pulse of higher amplitude might be used to reverse the process by thermal means or for the Ta/TaO or Ti/TiO in an oxide matrix nano-particle example model a current pulse in the opposite direction would be used, with some degree of compliance. It is obvious without compliance that the process would result in barriers on the opposite leading edge and the same value of resistance.
Fabrication has to be considered; I would suggest something like depositing alternate films, allowing the nano-particle layer to aggregate into clusters that will form the nano-particle. Although in Figure 1 we have used the egg yolk structure, other structures such as platelets may be more appropriate, or even carbon or other material nano-tube shaped structures.
To create the required narrow inter-particle gaps in a randomly distributed 3D structure, the volume fraction of nano-particles would most likely need to be close to 33%. If the nano-particles are conducting, then the probability of short circuits becomes unity. That leads to the conclusion that the nano-particles would initially have to be non-conducting. The insulating surface layer would then narrow the gap and deplete the conducting matrix material of one element to render it less conductive.
What is the definition of a “bulk switching"? If a memory cell structure is reduced in size so as to have to same dimensions as a filament it could be claimed to be a bulk effect. If interface memory effects are stacked then one could describe any observed memory phenomena as a bulk effect.
Let’s explore such a possibility for a Ti/TiO-MnO interface: As illustrated in figure 2(a), a simplistic description of the operation of the device oxygen is moved into the metal oxide layer that create vacancies in the MnO oxide. This creates a barrier to holes trying to traverse the interface. It is highly likely that rather than being a perfectly planar process island-like barrier regions or platelets are created which then expand. For constant current write the increase in current density in the inter-barrier regions will accelerate the barrier formation until the hole conduction across the interface is completely blocked. This is illustrated in Figure 2(b).
This leads to a solution that might possibly offer shorter write time. In this implementation nano-platelet barriers are created and removed during write/erase, without any need to create them during fabrication or the need for an electrical forming step – unacceptable for any type of memory.
The proposed memory cell structure is shown in figure 2(c). It consists of repeated thin layers of metal-the metal oxide and an oxide of a manganese oxide compound, for example. During write, the island barriers start to form. This localizes the current so that in the next layers above the barrier forms directly above the space between the barriers below. The write process does not have to complete the barrier over the whole surface, saving write time, as the convoluted current path between the barriers results in a high resistance state for read. A reverse current pulse removes the barriers in the normal way. That fabrication is simple: just multiple layers with no need to aggregate nano-particles as described in my earlier paragraphs.
If we are going out in left field for new idea, nano-sized solid-state electrochemical plating baths have already been suggested by Micron as a non-volatile memory (Cu in CuTe). What about the possibility that each cell is a nano-battery and charging and discharging it provide the two memory data states? Its output voltage then provides a ready-made read signal. Perhaps we leave that to others for the moment.
Has Intel used any of these speculative solutions for 3D XPoint? Who knows? Perhaps the speaker at the launch presentation who triggered this speculation was not really trying to convey the idea of structural depletion effects.
As if to pour cold water on our speculative fun, just as I was wrapping this article my attention was drawn to a Micron job advert posted on July 28, 2015 indicating that Micron R&D has an immediate need for engineers to support the development of advanced PCM-based non-volatile memory products. Based on the timing it is not unreasonable to consider this might be some evidence that 3D XPoint and Micron's follow on equivalent products might well be some form of born-again PCM, or it could be for some continuing research and development completely unrelated.