The new GPAK5's asynchronous state machine (ASM) block is equivalent to having a simple microcontroller (MCU) running approximately 100 lines of code.
In March 2015, Silego introduced its GPAK4 family (see Teeny-Tiny GPAK4 mixed-signal FPGAs for embedded systems).
As I've mentioned before, I tend to think of these GPAK chips as super-small mixed-signal FPGAs that you can literally design and program in just a few minutes, and that cost only a few cents each. GPAK mixed-signal FPGAs allow you to replace a number of off-the-shelf "glue" chips and gather their functionality into a single low-cost device. In addition to minimizing the component count and reducing costs, this shrinks board size and reduces power consumption.
Now, Silego has announced its next-generation GPAK5 family, which features a number of new and enhanced functionalities, including a zero static-power asynchronous state machine (ASM) block, an 8x8 scratchpad memory, and an I2C block. These new functions, along with the configurable digital and analog fabric seen in previous GPAK generations, are all presented in a tiny 2.0 x 3.0 mm 20-pin STQFN package with 18-GPIOs.
The ASM block will be of interest to many designers. Being asynchronous, this machine only operates in response to a change on one of its inputs. When it's not transitioning from one state to another, it consumes zero power (apart from ~1 nA of leakage current).
The ASM boasts eight states with 24 inputs (three per state) and has been implemented in such a way as to ensure no metastability issues, no race conditions, and full determinacy, even when multiple inputs transition simultaneously. As with all GPAK devices, the ASM is configured and connected to the rest of the device's functions using Silego's intuitive GPAK Designer graphical user interface.
Another way to think of this ASM is as it being equivalent to having a simple microcontroller (MCU) running approximately 100 lines of code, except that it's much easier to capture the desired functionality.
Also of interest to many designers will be the new I2C block. Like all GPAK devices, the GPAK5 includes an OTP (one-time programmable) NVM (non-volatile memory) containing the configuration; this is coupled with RAM that actually configures the functional blocks and the interconnect. When the device is powered up, the contents of the NVM are automatically copied over into the RAM.
In the case of the GPAK5, the I2C block can be used to reconfigure the contents of the RAM after power-up. This capability can be used for something as simple as "tweaking" analog comparator threshold values and modifying time delay settings, all the way to fully reconfiguring the entire device. It's also possible to initiate a remote software reset by using the I2C to write a particular bit, which causes the device to reload its RAM from the NVM.
Furthermore, in addition to providing the capability to read the values on all of the input pins and directly control the output pins (up to eight pins) via I2C, it's also possible to use the I2C to drive up to eight "virtual inputs" into the GPAK5's connection matrix.
It's going to be really interesting to see how designers use these new capabilities. In the meantime, for pricing, samples, datasheets, and technical information about these devices and the GPAK Designer software, you can contact Silego's customer service team at firstname.lastname@example.org or visit the website at www.silego.com.
— Max Maxfield, Editor of All Things Fun & Interesting