In order to achieve accelerated FPGA development schedules, designers require the aid of sophisticated synthesis tools.
FPGA device density is continuing to grow at approximately 2x per node, which is -- not surprisingly -- driving larger, more complex designs. This means that FPGA designers face several challenges as follows:
- Longer run times due to increasing design size and complexity.
- Achieving rapid synthesis turn-around time to integrate design changes.
- Avoiding unnecessary resynthesizing of pre-verified, static modules, like IP blocks and completed modules.
In order to achieve accelerated FPGA development schedules, while supporting increasing design sizes and complexity, designers require the aid of sophisticated synthesis tools.
Many years ago, Synplify FPGA synthesis software introduced a capability that allowed designers to automatically or manually create RTL partitions ("compile points") in their FPGA designs. Designers utilizing compile points could develop modules separately, add incremental features to be incorporated, and complete incremental synthesis of designs. This boosted productivity and design closure because it allowed designers to synthesize a module once, and only resynthesize those parts of the design that changed.
Figure 1. Fast initial and incremental runtimes using compile point technology (Source: Synopsys)
However, there is a growing need to further accelerate runtimes beyond what the compile point technology provides. Newer, larger devices are lengthening runtimes significantly, and designers are finding that they need synthesis tools that enable much faster runtimes to achieve their design schedules. This translates to the number of iterations-per-day designers can achieve to support incremental changes to the full FPGA design, which are a necessity to support hardware validation and accelerate the development of embedded software. The latest version of Synplify provides customers with advanced distributed synthesis technologies that provide a 3x boost in runtimes and productivity. Distributed synthesis takes the compile point concept to the next level -- employing distributed processing across multiple cores and multiple machines -- throughout the entire synthesis flow for easy deployment to server farms.
Figure 2. Enabling server farm distributed synthesis with multiprocessing (Source: Synopsys)
As the overall FPGA design increases in size and complexity, Synplify provides a scalable flow that is able to handle increasing design complexity and sizes. In conjunction with faster runtimes with distributed synthesis, the overall memory footprint is decreased.
The Synplify compile point flow allows parallelism in processing; however the achieved benefit is limited. The distributed synthesis technology allows designers to design much larger and complex FPGA designs while continuing to accelerate runtimes. This provides a significant productivity gain and helps to achieve the ever shrinking design schedules. As FPGA designs become bigger and more complex, distributed synthesis becomes the obvious choice for creating FPGA designs quickly.