In theory, physical synthesis tools have all the necessary information about the layout; in practice, they must be correlated very carefully to real-world layout data.
The design of a chip involves many stages, from system specification and architectural design, all the way to the fabrication and packaging of the final silicon that goes into a device. During this cycle, it is crucial to have reliable estimates of timing and area in order to plan properly and meet expectations. This article will take a look into the physical design (or backend design) portion of the process; specifically, at the correlation of timing and area within the steps associated with the physical design.
Integrated Circuit (IC) design flow and physical design steps (Source: CEVA)
Correlation problems between synthesis and placement
Large designs may take many days to run through the full physical design flow. Thus, it is valuable to have the ability to give early feedback to the design and architecture teams, to develop timing constraints, and to have the freedom to explore floorplan options quickly. In order to achieve these goals, it's imperative to have reliable estimates of timing and area.
In the past, we've had reasonably good correlation between synthesis placement and route. For timing, the accuracy would be around 3% to 4%, with even better results for area. In new and advanced processes, however, starting at the 28 nm process node, we've been experiencing more and more cases of unexpected results. Not only have we seen larger gaps between the physical synthesis results to the actual timing in placement-and-route, but some timing paths became significantly faster, while others became much slower. This was quite puzzling. When looking at the area, the results were even more alarming. From synthesis to layout, the correlation had become quite poor, as illustrated in the following image:
Synthesized cell density in the floorplan stage (top) as compared to the placement stage (bottom) (Source: CEVA)
The above images are cell density maps taken from the CEVA-XM4 core, comparing the cell density in synthesis (top) to the cell density at placement (bottom). The orange sections in the placement image show a critical increase in area. The overall increase in area, in this case, was around 18%. This is quite bad, but perhaps not intolerable. However, after taking into account that most of the design is fixed area (memory and registers), which does not change at all from synthesis to layout, it becomes clear that certain parts are really going through the roof. When we isolated the buffer cells areas, we observed an increase of 118% over the synthesized area, meaning that the buffer count and area had more than doubled.
In the areas of extreme cell density (marked in orange), the placement tool finds it difficult to determine legal placements for the cells and performs multiple iterations, thereby requiring a significant amount of time to converge.
Exploring ways to improve timing and area correlation
A first attempt to tackle this issue was to tighten the frequency. In other words, we tried to synthesize at a higher frequency and then switch to a slightly lower frequency during place-and-route. This solution did not solve the problem. Another attempt was to derate the timing of nets and cells. Derating is, in effect, adding coefficients that make the cells slower or faster, and we experimented with several numbers. An additional direction that we've explored is to get a better correlation on extraction numbers. This is done by applying coefficients to the extracted resistance and capacitance (RC) values of nets. These values directly affect the delay of nets by changing their RC values, and consequently affect the delay of cells by altering their load capacitance.
From an electrical engineering perspective, we know that as the process shrinks, resistance becomes more dominant. On the one hand, capacitance of the wires stays roughly the same (or at least within the same order). On the other hand, the resistance becomes much, much higher. In addition to this, in advanced process nodes, the topmost two metal layers have much lower resistance than the rest of the layers. In turn, this means that deciding which wires will go to the higher layers and which wires stay on the lower layers becomes much more problematic for the layout tools. Most affected, of course, are long nets that are buffered. This is why there is such a significant increase in buffer area and degradation in timing associated with long nets.
Synthesized cell density in floorplan stage (top) as compared to the placement stage after applying coefficients (bottom) (Source: CEVA)
We have found that increasing the resistance gives much better area correlation and timing correlation. The factors by which to achieve good correlation vary from design to design. As shown in the image above, after applying the coefficients to the resistance, the correlation between synthesis and placement significantly improved. Again, we compare synthesis area (top) to placement area (bottom). There is still a significant load of high utilization, as seen in the orange area in the placement image, but much less than before. In this example, the accuracy achieved was about 5%, which is quite reasonable and which enables a good and efficient work flow.
Putting the results to use
What we have seen is that resistance has a huge effect on timing and area in advanced processes. Although, in theory, the physical synthesis tools have all the necessary information about the layout, they still must be correlated very carefully to real-world layout data. This process may be time-consuming, but the benefits clearly outweigh the costs. At the end of the day, the best practice is to maintain a trustworthy correlation between the various steps of the design flow; to gain fast, flexible designs; and to generate a clear view of the end, from the beginning.
Click Here to download the Improving Timing Correlation to Synthesis in Advanced Process presentation by Sharon Berlowitz, and Click Here to download the CEVA-XM4 white paper.