Multiple patterning is an innovative approach to scaling semiconductors, but it also poses significant challenges controlling process variations.
Multiple patterning is a method for enhancing feature density by producing finer resolution than can be achieved with a single lithographic pass. It has been proven in volume production as an effective method for pitch-shrinking, with 2x to 4x reductions now standard, and will continue to be a key element for success even with EUV in the future.
However, to achieve production-level success with multiple patterning engineers must understand and control inherent process variations that result from increasing number of process steps.The basic challenge is that with more process steps, there are more sources of variation.
In self-aligned multiple patterning schemes, critical dimension (CD) variability is impacted by variation not only from litho, but also from etch and deposition. For example, in self-aligned quadruple patterning, variations from litho, deposition, and etch could result in three different CDs, an undesired result known as pitch walking. To meet scaling requirements, variation from each step must be reduced in order to minimize pitch walking and produce the minimum on-chip device variation.
There are multiple sources of variability to be managed: within die, within wafer, from wafer to wafer, and from tool to tool. Within a die, the primary sources of variations come from geometry, pattern loading, and line edge roughness (LER). Within a wafer, variations are caused by the electrical and chemical gradients from center to edge across the wafer during processing. Wafer-to-wafer and tool-to-tool variations are determined by how tightly the hardware and process are controlled. Reactors are highly sophisticated and complex machines with countless sources of variability.
Within a die, line edge roughness is one of the key contributors to variation. Plasma etching is well established as a technique to reduce roughness in defined patterns. At a microscopic level, medium- and high-frequency LER appears as protrusions and divots in the exposed pattern. Sharp protrusions offer a higher surface-to-volume ratio and therefore are preferentially etched laterally by plasma reactants. In addition, deposition process gases and byproducts tend to fill in small divots. This combination leads to an overall reduction in line edge roughness.
On the wafer scale, etching provides an opportunity to correct for incoming material variation by creating a high-spatial-resolution, non-uniform temperature profile. By altering the wafer temperature locally, the probability that passivants stick to the sidewalls of the etch feature can be modified. Higher temperatures lead to less passivation and smaller CDs, while lower temperatures result in more passivation and larger CDs. Thus, temperature can serve as a tuning knob to compensate for incoming CD variability and reduce the final within-wafer CD variation. By pre-measuring CDs coming into the system and feeding that information forward to the temperature controllers, CD non-uniformity after etch can be reduced by as much as a factor of three.
As device feature sizes are approaching the atomic level, atomic layer deposition (ALD) and atomic layer etching (ALE) are being used to reduce variability further. In self-aligned multiple patterning schemes, spacer thickness control is critical in determining CD. ALD is then used to produce perfectly conformal and uniform spacers. Similarly, ALE can be used to eliminate dependency of profile, CD, and etch depth on feature dimensions and pattern loading. ALE has the added benefit of enabling surface smoothing.
In summary, a number of solutions have been developed to reduce variations with multiple patterning. While these techniques have proven valuable in reducing variability and thereby enabling the continuation of scaling, they usually entail higher processing costs, and the cost problem remains an opportunity for further collaboration between equipment makers and semiconductor manufacturers.
--Richard Gottscho is executive vice president of global products at Lam Research Corp.