New semiconductor technologies like FinFETs are giving rise to new types of fault effects not covered by standard stuck-at and at-speed tests.
Automatic test pattern generation (ATPG) tools perform two key functions: (1) they generate stimulus/response patterns used by automatic test equipment (ATE) to determine whether or not a digital or mixed-signal design is defective, and (2) if the design is defective, they isolate the probable location of the fault(s). For decades, ATPG has proven a reliable workhorse in performing these functions, but now a young, sleek stallion has come to pasture -- in order to accommodate recent trends in the semiconductor industry, Synopsys has re-engineered ATPG from the ground up to be smarter and more efficient.
One of these trends is the growing deployment of FinFET process technology for SoC designs. Though opinions differ on whether FinFET intrinsically requires special testing versus FDSOI or other MOSFET technologies, the circuit dimensions are so small (16nm or less) that on-chip process variations can affect transistor sizes, threshold voltages, and wire resistances. These variations give rise to new types of fault effects not covered by standard stuck-at and at-speed tests.
Innovations in ATPG fault modeling technology are now making it possible to target these fault effects and thereby achieve the same low defective parts per million (DPPM) levels semiconductor companies have long come to expect. Using "cell-aware" fault models, for example, ATPG can target extremely subtle FinFET defects such as a resistive open on a fin. Dynamic bridging and hold-time are other examples of advanced ATPG fault models being introduced to address these challenges.
Another trend is automakers' increasingly stringent quality requirements -- often less than 1 DPPM -- reflecting the degree to which ICs that go into safety-critical systems such as advanced driver assistance systems (ADAS) depend on high defect coverage to minimize the risk of failures that could cause injury or damage.
An ATPG technology known as "slack-based test," designed to meet ultra-low DPPM requirements, is ideally suited for ICs that compose safety-critical systems. Unlike standard at-speed testing, slack-based testing uses slack data generated by the Synopsys PrimeTime static timing analysis tool to target delay faults along paths with minimum slack, thereby ensuring passing ICs will function correctly at the operating frequency designed for the part.
A third trend is the demand for fast ramp-up to high yields for emerging processes (think 10nm and 7nm nodes). This trend reflects the sense of urgency foundries and semiconductor manufacturers have when it comes to bringing up new processes to capitalize on the growth potential of the global IoT chip market, which is expected to reach $10.8 billion by 2022 (Research and Markets: Analysis, Technologies & Forecasts Report 2016-2022).
Accelerating yield is feasible if one can quickly and inexpensively pinpoint the location of silicon failures. Physical failure analysis (PFA) engineers are accomplishing this with new cell-aware ATPG technology that combines detailed knowledge of cell layouts, internal defect behaviors, and timing-critical paths to increase diagnostics resolution down to the transistor level. Moreover, increasingly tight links between cell-aware diagnostics and yield analysis solutions are now letting PFA engineers determine the root causes of defects in hours instead of days or weeks.
The use of advanced fault models to lower DPPM and improve diagnostics resolution nonetheless leads to longer ATPG runtimes and more patterns, outcomes compounded by ever-higher design complexity (over 5 million placed instances are common). ATPG therefore needs to be more pattern-efficient to minimize the cost of applying these types of tests on the ATE, and it needs to be an order-of-magnitude faster to avoid impacting project schedules.
Multicore processing is a step in the right direction, although the memory overhead of requiring each core to manage its own virtual fault list creates memory bottlenecks that can leave some cores under-utilized (Figure 1).
Figure 1. High ATPG memory consumption limits the number of cores being utilized (Source: Synopsys)
Synopsys' new TetraMAX II ATPG and diagnostics solution reduces the required memory per core (Figure 2) by generating thousands of "iCubes" (i.e., fault activations) in parallel on multiple cores. It then intelligently combines them to create fewer patterns.
Figure 2. Memory usage vs. speed-up (by adding cores) (Source: Synopsys)
These (and other) optimizations deliver about 25% fewer patterns and 10X faster ATPG execution than previous technologies, thereby allowing designers to reduce the time and cost of testing silicon parts, or to increase test quality without impacting test cost.
In summary, breakthrough innovations in ATPG technology have arrived. TetraMAX II ATPG now leverages detailed timing and physical information to enable ultra-low DPPM and ultra-high diagnostics resolution. Although higher test quality invariably comes at the expense of pattern count and runtime, the latest technology uses highly optimized, memory-efficient methods to minimize pattern count and speed test execution. Bring on the stallion.
Chris Allsup is Senior Staff Technical Marketing Manager in the synthesis and test group at Synopsys. Chris has more than 20 years combined experience in IC design, field applications, sales, and marketing.