TechInsights explores SK Hynix's U-shaped NAND cell architecture.
The SK Hynix 3D NAND (version 2) cell structure has a U-shaped vertical NAND string with pipe gates (or back gates) on the bottom portion, which is totally different from the DC-SF vertical NAND structure they showed in 2010.
Figure 4 shows the SK Hynix 3D NAND array structure. We may be able to name it as a SMArT; however, more properly speaking, their new 3D NAND structure is quite different from the SMArT architecture.
Figure 4. SK Hynix 3D NAND array structure with U-shaped NAND string (SEM Image) (Source: TechInsights).
The SK Hynix 3D NAND uses an ONO (oxide-nitride-oxide)-based charge trap flash (CTF) and gate all around (GAA) for each cell transistor, but they adopted the U-shaped vertical NAND string. The pipe gates are on the bottom portion to connect two different vertical strings, which is a similar architecture to P-BiCS proposed by Toshiba in 2009. At that time, Toshiba’s P-BiCS Flash was developed to improve their previous BiCS Flash technology, such as reliability of memory cells, cut-off characteristics of the lower select gate, and high resistance of source line. Toshiba changed the vertical NAND string from a straight shape to a U-shape.
As with Toshiba, SK Hynix likely uses the U-shaped vertical NAND string for better data retention, wider Vth window, lower resistance of source line, and better-controlled cutoff characteristics of the select gate.
Another keyword from the SK Hynix U-shaped vertical NAND cell array is a floating Si body layer for pipe gates (PGs). An insulating layer separates the silicon body with the pipe gates or pipe connections from the substrate. Source lines (SLs) and bit lines (BLs) are located on top of the vertical cell array. Drain select line (DSL) and source select line (SSL) with three stacked transistors are placed under the SLs and BLs.
The 43 stacked gates on the pipe gates likely consist of 36 memory cells, DSL/SSL with three drain select transistors (DSTs)/source select transistors (SSTs) and four dummy wordlines. The ONO-based CTF is used with a macaroni-type Si channel and W control gate. The doped region is under pipe connections.
Two different slits are used for process integration: one is on the pipe gates, and another is on STI as a block slit. Slit height is measured as 2.39 μm. Three metals are used, such as metal 1 (W), metal 2 (Cu), and metal 3 (Al), while Samsung and Toshiba/SanDisk use four metals. Two-step BLPs are used as well. Table 2 summarizes the quick view on SK Hynix 3D NAND cell structure.
Table 2. Summary of SK Hynix 36L 3D NAND memory cell structure (Source: TechInsights).
According to a quick review of SEM images of SK Hynix 3D NAND cell structure, the process integration for the vertical NAND cell structure likely follows an STI/PG formation followed by a channel hole process, including a storage layer and channel hole filling, and then a slit process, gate replacement, SLs and staggered plugs, and BL formation follow.
Two vertical channels are connected through two pipe gates (or pipe transistors) which are used to improve the flow of cell current in the NAND string. The SK Hynix 3D NAND version 2 with 36L is the product using the U-shaped vertical NAND string for the first time. SK Hynix announced that their 3D NAND version 3 with 48L would be revealed in the market as well this year.
Now we can say that 3D NAND cell architecture is mainstream in the market. All of the 3D NAND players have their own unique cell structure, including FG-based and CTF-based cells. Which one would be better for 128 or higher stacked 3D NAND from the process integration and reliability viewpoint may be revealed in a couple of years.
Please don’t miss out on upcoming TechInsights’ analysis on 3D NAND products. For more information on the analysis featured in this article, please visit us here.