The time is ripe for a new direction to take advantage of the unique features of PCMs/RRAMs as single component pulse integrators with the non-volatility and plasticity that make them attractive as possible synapses and neurons in learning machines.
Part 2 of two-part report
The possibility that MRAMs will be the memory technology of choice for persistent memory and be the preferred non-volatile DRAM replacement is real and something those working on PCMs/RRAMs must take seriously. The time is ripe for a new direction to take advantage of the unique features of PCMs/RRAMs as single component pulse integrators with the non-volatility and plasticity that make them attractive as possible synapses and neurons in learning machines. IEDM 2016 continued its role of providing a platform for those demonstrating the effective use of those characteristics for brain-like functions and giving us a glimpse of possible brain-gate or brain-gate array components of the future.
An international team from Milan Polytechnic, Italy and Micron, Boise Idaho [Ref 1] provided an update on the their work using RRAMs for unsupervised learning. Unsupervised learning is the ability to learn and recognize random patterns. Supervised learning would be learning the images of say traffic lights and hand writing.
The team offered solutions for spike-time dependent plasticity (STDP) and spike-rate dependent plasticity (SRDP) with a RRAM at the core of each circuit solution. The evolution of their three brain-gate circuits is illustrated in Figure 1 with in each case a RRAM as the core component.
Figure 1(a) is the the circuit used for learning time dependant patterns. The principle is simple, the PRE synaptic pulses are summed and input to the integration circuit. When a PRE pulse causes the integration circuit to pass a threshold voltage it outputs a positive followed by a negative spike to the RRAM which acts to either SET or RESET the RRAM.
In-sync PRE pulses will provide the largest contribution to the integrator and will have a highest probability of resulting in the POST output pulses and be present on the input to the RRAM when the positive POST pulse appear. This will result in long term potentiation (LTP).
Any PRE synaptic pulses arriving during the time when the negative part of the POST pulse is present will cause the RRAM associated with that synapse to be reset or undergo long term depression (LTD). The result is over time RRAMs associated with in-sync pulses will experience LTP while all others will suffer LTD. Or in the perhaps more familiar language of the RRAM electronics have the resistance decreased or increased.
Figure 1. Source: Ron Neale
The circuit of Figure 1(b) addresses the problem of recognizing patterns that are rate dependent. For this the PRE pulse and a delayed version of it are delivered to the integration circuit via a NAND gate marked M1 and M2 (where the truth table is determined by the current delivered to the integrator). The coincidence of two pulses at the NAND gate will cause the largest current pulse to the integration circuit, which will result in LTP if a positive pulse is applied to the RRAM. An event more likely to occur when the average pulse rate is equal to the reciprocal of the delay time. For pulses arriving at the synapse with a separation in time different from the delay time will not result in LTP.
When the PRE pulses are arriving at the left hand NAND with a large spacing significantly different from the delay time that NAND circuit will be inactive. During that time LTD is achieved by using noise pulses of two different frequencies applied to the NAND gate on the right in figure 1(b), marked as M3 and M4. The noise pulse spikes of a frequency f3 are applied to M3 and the noise pulse output of the integration circuit is applied as a negative pulse to the RRAM and after inversion to M4.
A judicious choice of the values of f3 and f4 ensures the system works effectively and the noise pulses do not come dominate the situation. The synapse experiencing pulses with a spacing significantly different from the delay time, will result in LTD, the RRAM will be reset. Figure 2 is an example of the learning over time reported by the team.
and shows the experimental and calculated demonstration of the time evolution of 8x8 synaptic weights for SRDP of their RRAM based neural network, the synaptic weights are recorded at epoch N = 1, 500, and 1000 of the learning experiments.
Their third brain-gate circuit was for the learning of grey scale images, which involved replacing the delay circuit with a frequency to voltage converter (FVC). Color was the achieved by the use of three neurons per pixel.
A very low voltage neuron.
A team from Centre for Nanoscale Materials, Argonne National Laboratory, University of Chicago, Purdue University, [Ref 2] described the use of VO2 threshold switches to create a low-Voltage artificial neuron using a feedback engineered Insulator-to-Metal-Transition.
The team set themselves the task, and succeeded, in providing the key aspects of a neuron: an integrate-and-fire capability, a threshold activated output waveform, and a post output refractory period during which the neuron does not integrate inputs. With a target of operation at voltages below 0.8V and with a minimum of supporting components.
For this work, as illustrated in figure 3(a) the team used their VO2 threshold switches as the pulse integration devices in a simple RC oscillator circuit 3(b). The lateral device structures utilized lengths and widths covering the rang from 0.5um to 20um with thickness of 200nm and to avoid side wall heat loss a photo-resist coating was employed as a sheath to cover the active material.
As illustrated in Figure 3 (c) in operation input pulses steadily increase the voltage across the capacitor until at its threshold voltage the device switches to a low voltage state. After firing and the discharge of the capacitor excess Joule heating causes the switch remain in its low resistance state preventing the voltage across it and the capacitor from rising and and integration ceases. It is this characteristic which accurately mimics the post-firing refractory period in a biological neuron. The integration of any incoming pulses recommences when when the refractory period is over and the switch returns to its high resistivity state and the VO2 has cooled down below the transition temperature.
Controlling, on-to-off resistance ratios and heat transfer characteristics provides the means to control the threshold voltage and the time of the post-firing refractory period. The rate of VO2 film deposition (oxygen stoichiometry), the choice of substrate (SiO2 or Al2O3) and device dimensions were the key experimental and simulation variables.
A generally applicable electrical-thermal model for IMT based devices was developed and verified from electrical measurements of VO2 devices, which was then used it for designing IMT based artificial neurons.
The work culminated in the demonstration of an artificial neuron with integrate-and-fire and post firing refractory period characteristics capable of operating at 0.8 V. with simulations which predict with scaling further voltage reduction sub 0.3Volt operation will be possible.
Brain gates the way to go
Late last year at IEDM-2016 Toshiba with Hynix announced plans for a 4Gbit MRAM and even although perhaps 3 to 4 years away from a commercial and proven product, plus the progress made by other MRAM vendors must be read as danger signals for PCM/RRAM product developers. It may be time for the PCM and RRAM communities to look at brain-gates as a potentially more rewarding future direction where their technologies will be able to offer unique features. Brain-gate: a circuit or array where the unique features of PCM/RRAM are integrated with conventional silicon.
Read Part 1 here.
—The career of Ron Neale, as a researcher, process developer, and designer of solid-state memory devices, stretches back over 50 years. More recently he has been involved as a consultant, writer, and keen and critical observer of the latest memory developments. His EE Times Progress Reports on the state of play in memory developments have a large following. He has a number of firsts in memory device development and manufacture in the areas of phase change memory (PCM) and programmable read-only memory (PROM), including anti-fuzes and programmable VIAS. He holds 20 patents in the area of memory and programmable interconnect and is a member of The Institute of Physics and a Chartered Physicist.He is also qualified as both a mechanical and electronic engineer. As well as memory device development and research, Ron has also held senior positions in companies involved in computer development and the manufacture of semiconductor fabrication equipment, as well as serving a stint as editor of Electronic Engineering magazine.
[Ref 1] Demonstration of hybrid CMOS/RRAM neural
networks with spike time/rate-dependent plasticity, V. Milo1et al, PROC IEDM 2016.
[Ref 2] Low-Voltage Artificial Neuron using Feedback Engineered Insulator-to-Metal-Transition Devices J. Lin et al, Proc IEDM 2016.