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Will Storage Class Memory Disrupt Memory Hierarchy?

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TravisOR
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Re: latency
TravisOR   1/20/2017 11:21:08 PM
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Instead of understanding SCM in a linear line in between NAND and DRAM, my article explains SCM in 2D plane - Performance vs. Cost

 

TravisOR
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Re: latency
TravisOR   1/20/2017 11:12:54 PM
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You are right. DRAM runs at about 35ns-40ns in general. Some speciality DRAM, such as HBM, works at 10ns. Though, NOR-based NVDIMM is pretty close to DRAM read latency compared to others. When storage memories are compared, 100ns read latency should be super-fast. 

resistion
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latency
resistion   1/20/2017 10:11:08 PM
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Not sure where the idea of DRAM latency being ~100 ns comes from, it should be 10 ns or less. That's why NOR/XPoint would find it hard to enter this area, despite cost effectiveness. It could fit between DRAM and NAND.

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