Tomorrow's exponential growth in semiconductors will be fueled by a combination of specialized processes and design methodologies as transistor scaling becomes increasingly expensive, said the chef technologist of Texas Instruments.
The International Solid State Circuits Conference (ISSCC) has been a celebration of CMOS transistor scaling. But in his ISSCC plenary talk TI’s CTO, Ahmad Bahai, asked to take a different view. Rather than count the number of transistors we can render in deep submicron CMOS, he described a combination of factors including clever design as well as specialized packaging.
Shrinking CMOS geometries are essential for smaller appliances and longer battery life. But mobile handsets are no longer the only application offering exponential growth. The next 20 years will offer a broader variety of exponentials, enabled by specialized design, processes and manufacturing.
Rather that depend on CMOS scaling, Bahai recommends a hands-on engineering approach harnessing multiple design techniques and specialize fabrication processes. The innovative architectures available to analog engineers include digitally-assisted analog, and systems-on-package with precision passives. Specialized processes available include BiCMOS in which higher power transistors are embedded on a CMOS digital substrate, silicon germanium (SiGe), silicon carbide (SiC), and gallium nitride (GaN) for power.
Combinations of these variables can enable electronics with exponential growth potential, Bahai insists. As an example of a market with only small dependencies on CMOS scaling, he uses mm-RF circuits for automotive radar processors whose transceivers are dependent on mixed technologies.
The mm-wave RF transceiver’s technical requirements include wide bandwidth, and beam forming which enables depth precision and material penetration. Scaled CMOS provides only limited gain here.
Multiple technologies along with specialized packaging enable mm-wave radar processors for cars while digital CMOS offers only substrate support for the circuits. (Image: TI)
Package metallization must be optimized for both improved passives, and to overcome the harmonic effects of coarse feature size in the packaging. The sensitivity of the automotive module is so great, Bahai notes, that it will not only detect and image on-coming cars, it can also image the driver’s breathing pattern.
Personalized medicine such as wearables is another application with exponential growth and a different set of requirements such as ultralow power consumption and disposability, Always on and operating in real time, a clinical glucose meter will enable adaptive sampling. Wearable bio-sensors offer more meaningful data than a simple heart rate, and again it does not necessarily benefit from CMOS scaling, he notes.
Power management applications are typically constructed around the tradeoff between power handling ability and switching speed. The tradeoff will be minimized, not by CMOS scaling, but with the use of specialized fabrication processes.
New generation power transistors include LDMOS, super-junction transistors, GaN, SiC, and integrated passives. Ordinarily, power transmission systems make do with slow-but-accessible switching frequencies. The rule is that the higher the voltage, the more sluggish the power transfer system will be. The newer transistor materials will enable high switching frequencies.
Silicon IGBTs, for example, now offer much higher than 600V breakdowns for industrial use but with relatively low switching speeds. Integrated silicon MOSFETs operate typically far below 600V ― below 20V in fact for computers ― but with 100s of MHz switching. Super junction Mosfets can operate below 1 Kv and SiC FETs operate up to 1.8 kv and can provide much higher switching speed , and GaN FETs operate below 600V and can handle switching speeds of 10s of MHz.
—Stephan Ohr is a former director for Semiconductor Research at Gartner, editor in chief of Planet Analog and an editor on EE Times.