What is 3D Super-DRAM and why do we need 3D Super-DRAM? The CEO of Besang makes the case.
Even though 3D NAND could not achieve low cost-per-bit compared with planar NAND yet, NAND has successfully transformed from planar to 3D. However, DRAM still remains at 2-dimension. In the meanwhile, scaling of DRAM becomes extremely difficult mainly because aspect ratio of storage capacitor exponentially increases as device shrinks. Therefore, in order to expand lifespan of DRAM, 3D DRAM must be required for the DRAM in short time.
Let me explain what is 3D Super-DRAM and why do we need 3D Super-DRAM. Planar DRAM has memory cells array on one side and memory logic circuitry on the other side. 3D Super-DRAM stacks cell array on top of memory logic. Therefore, die size becomes small and we could produce more die-per-wafer. It means 3D Super-DRAM is much cheaper than planar DRAM.
3D Super-DRAM reuses proven process flow and device structures being used in planar DRAM. When we compare planar DRAM and 3D Super-DRAM, storage capacitor and memory logic circuitry should be the same. The only difference is cell transistor. Planar DRAM normally uses recessed transistor and 3D Super-DRAM utilizes vertical SGT. The difference will be discussed.
The most important and difficult challenge for planar DRAM is the high aspect ratio of storage capacitor. As shown in the graph, the aspect ratio of storage capacitor is growing exponentially as device shrinks. In other words, device scaling of planar DRAM is becoming extremely difficult. As we understand, DRAM scaling is being slow down and manufacturing cost is rising abruptly mainly because of scaling of storage capacitor. So, what do we do with storage capacitor? We will not change or modify storage capacitor used in planar DRAM. Though, we could achieve 400% more die-per-wafer using cell stacking technology of 3D Super-DRAM. Because storage capacitor is reused, multi-billion dollar R&D for the development of new storage capacitor is not required. So, fast time-to-market is enabled. Also, there is no risk involved with advanced storage capacitor development. Again, 3D Super-DRAM stacks cell array on top of memory logic and produces 400% more die-per-wafer using existing storage capacitor. It enables fast time-to-market and drastically reduces cost for R&D.
Let me compare the characteristics of vertical SGT and recessed transistor. Both of them are good for scaling of distance between source and drain in order to minimize source and drain leakage current. Vertical SGT controls gate at all directions. So, it has better subthreshold characteristics compared to recessed transistor. At high temperature, it is well known that SOI has about 10 times less junction leakage current. One downside of vertical SGT is that no back-bias is available. Overall, both of them work well for minimized leakage current.
Here is comparison of parasitics of bit line. Buried bit line of planar DRAM reduces parasitic capacitance between storage capacitor and bit line. Vertical SGT is also very efficient to minimize the parasitic capacitance because bit line is located at the bottom of vertical SGT. Metal line is used for the bit line of vertical SGT and buried transistor. Therefore, series resistance of bit line can be minimized. Overall, performance and characteristics of vertical SGT and recessed transistor are about the same.