What is 3D Super-DRAM and why do we need 3D Super-DRAM? The CEO of Besang makes the case.
However, vertical SGT is extremely simple compared to recessed transistor. Vertical SGT needs only 2 masks. So, it saves 3-4 mask steps. For example, no source and drain mask, no recessed gate mask, no word line mask, and no buried bit line mask are needed for vertical SGT. If you have impression that 3D Super-DRAM is expensive to make, that is not right. Process and structure of 3D Super-DRAM are successfully verified. Device functionality and reliability are also well verified.
Here is the summary. 3D Super-DRAM enables 400% more die-per-wafer with simple process, minimized uncertainties, and fast time-to-market. If you consider planar DRAM shrinking from 18nm to 16 nm, then, 20% more die-per-wafer could be achieved. To do so, multi-billion dollar should be invested for R&D and EUV must be required. In case of 3D Super-DRAM, it needs less than $50M for R&D and no EUV; even so, it could produce 400% more die-per-wafer.
<[?Scaling of planar DRAM becomes extremely difficult mainly because aspect ratio of storage capacitor exponentially increases as device shrinks. As planar NAND faces its scaling limitation and is successfully transformed to 3D NAND, planar DRAM should find out its path to 3D DRAM in short time. Otherwise, lifespan of DRAM will end in few years.
—Sang-Yun Lee is the CEO of BeSang. Inc. BeSang is open to collaborate with system makers to introduce 3D Super-NOR NVDIMM to the market.
>>So, DRAM market is highly vulnerable. A diruptive technology could easily take majority DRAM market share. <<
The underlying assumption that the the three major DRAM vendors will sit still and watch someone try to take a majority market share is questionable at best. It is difficult to do DRAM at 1x and it is difficult to do 3D anything, DRAM or NAND. No one will come in without actual production experience and start making 3D DRAM without the Three Amigos noticing and quickly reacting. Building a fab for that ambition would be a recipe for losing billions of dollars.
Of course, the Chinese government has built large cities that remain ghost cities, monuments to foolishness. I suppose anything is possible, including building a ghost fab.
I also think DRAM will continue its scaling. Though, transition will be much slow because technical challenges are growing exponentionally and scaling of DRAM is not economically favorable due to high manufacturing cost. Much anticipated and delayed EUV should be required for advanced DRAM manufacturing below 15nm.
DRAM market is about $45 billion and recently revenue growing becomes so fast because of limited supply and less competition. So, DRAM market is highly vulnerable. A diruptive technology could easily take majority DRAM market share.
NAND vendors claim that they are building many layers of 3D NAND. However, there is no public information about cost-per-bit of 3D NAND. Based on SSD market price, there are about 10% to 30% price difference between planar-based and 3D NAND-based SSDs. So, the price difference of planar and 3D NAND components might be 15% to 50%, I guess. Please feel free to correct me if this estimation is wrong.
I think many will take issue with your claim that 3D NAND has not achieved lower cost/bit than planar NAND yet. Likewise 18 and 16 nm DRAM are already being done rapidly in succession in the same places, and 1z is already being planned. Not to discourage the consideration of SGT, but the mainstream is moving very fast.