An automatic test equipment (ATE) PCB (a.k.a. a test board) is at the heart of all major test activities targeted at verifying a specific semiconductor chip's functionality.
Semiconductor chip technology has become so advanced that testing these highly complex devices must be performed effectively to ensure high reliability and functionality. This allows chipmakers to convey to their OEM customers their highest confidences that their products are of the foremost quality and have been verified to operate according to their specifications.
An automatic test equipment printed circuit board, or ATE PCB -- serving as an interface to a large test system -- is at the heart of all major test activities to verify a specific chip's functionality.
Fig. 1. An ATE PCB serves as an interface to a large test system (Source: Teradyne, Inc.)
This assures chipmakers their semiconductor products are good-to-go to an ever- burgeoning chip market led by newcomers, such as Internet of Things (IoT), wearables, handheld devices, and other similar products.
ATE PCBs are designed and assembled to test an array of different semiconductor chips, including microprocessors (µPs), memory, system-on-a-chip (SoC), field-programmable gate arrays (FPGAs), and others. However, an ATE PCB is designed and assembled specifically to test one particular kind of chip set. Some of today's highly advanced chips bring tens of millions of dollars into a chipmaker's coffers.
In order to achieve that highly-prized chip-testing quality for chipmakers, a group of experienced program and project managers and highly-trained and savvy engineering personnel in ATE PCB assembly are of paramount importance. The requirements for disciplined administration management and assembly line technical knowhow are above and beyond that required for conventional PCB assembly. Considerable monetary loss and lost time-to-market are incurred if there's a misstep along the way toward successful assembly completion of an ATE PCB.
It's important to note that ATE PCBs differ from conventional industrial and commercial PCBs in multiple ways, but can be categorized in three main and different ways -- larger sizes, number of layers, and extra processes required, such as assuring the device-under-test or DUT site of an ATE PCB is highly reliable, extremely robust, and free of assembly process residuals and debris.
What makes an ATE PCB different also makes it difficult. Therefore, ATE PCB program managers must have extra knowledge going beyond that of conventional PCBs, plus have a good grasp of all ATE PCB associated nuances. Their main duties include understanding unconventional diagrams and illustrations, which are the hallmark of ATE projects.
Further, to effectively communicate with semiconductor company customers, program managers must be intimately knowledgeable of the lexicon and acronyms associated with ATE PCBs, of which there are many. They must also be well-versed on all hardware and input requirements relating to ATE PCB assembly, as well as knowing the various ATE PCB assembly processes, plus they must be capable of fluent, unambiguous communications with assembly engineering.
On the assembly side, technical personnel must have a high-level skill set and knowledge base of the various types of paraphernalia that goes on an ATE PCB. This includes such items as cables, stiffeners, tester configuration and orientation, and relevant hardware. Customer ATE PCB design electronic format input is a secondary area both program managers and assembly engineering must fully understand.
In this case, that input is unlike the usual netlist conventional PCBs use. Instead, customers provide that input in the form of bitmaps, map drawings, or ball maps. Therefore, program managers and assembly engineers must be highly adept at translating that original data and creating an appropriate netlist from these unconventional methodologies.
Aside from savvy program managers and assembly engineering, a highly accurate ATE PCB pick and place system, proper thermal profiling, solder sample, stencil design, and an aqueous type of cleaning process are the keys to successful ATE PCB assembly.
ATE PCB Machine
Fig. 2. shows an ATE PCB pick-and-place system. This is unlike the ones used for conventional large-size PCBs measuring 12 x 10-inches or 14 x 14-inches. Just the opposite, an ATE PCB pick-and-place machine must have the capabilities for handling larger footprint boards such as 20 x 24-inches, all the way up to a maximum size of 26 x 30-inches.
Fig. 2. An ATE PCB pick-and-place machine is capable of handling larger footprint boards, such as 20 x 24-inches, all the way up to a maximum size of 26 x 30-inches (Source: NexLogic Technologies)
Pick-and-place systems like these are highly accurate and extremely precise. For instance, today's most advanced versions provide features like 32,000 components per hour (CPH) placement and 21micrometer (µm) fine pitch repeatability. Fine pitch repeatability refers to placement accuracy of ultra-fine pitch devices.
A larger than usual reflow oven is a must-have companion for the ATE PCB pick-and-place machine. Here, the reflow oven features a greater than the usual 20-inch wide opening. It's also nitrogen compatible to create perfect solder joints. With nitrogen, the solder wicks to the center of the pad to form the perfect joint.
Selective or spot soldering is another distinguishing feature of an ATE PCB pick-and-place machine. In some cases, through-holes are used as part of a board assembly. Selective soldering is used in these instances to assure that through-hole components are perfectly soldered.
Unique Thermal Profile
Every ATE PCB going through assembly will have a unique and specific thermal profile. ATE boards are larger in size than conventional industrial or commercial PCBs. It's not uncommon to see 20 x 22-inch, 22 x 24-inch, or -- in some cases -- 24 x 30-inch boards.
Typically, in the ATE world, these PCBs have a number of power and ground planes or layers. For comparison purposes, a network PCB could have 12, 14, or -- sometimes -- 20 layers. But an ATE PCB can have 36, 40, 50, or -- in some cases -- even 60 layers. This means there may be as many 40 power and ground layers and 20 routing layers.
Between every two routing layers, there is a ground layer and then a subsequent power layer. Due to these power and ground layers, they are typically full layers and not the trace layers. The bottom line is that, due to the large number of power and ground planes, an ATE PCB requires considerable heat during the reflow process.
A highly specific thermal profile is thus required to heat up the entire board. It has to be so specific that it doesn't damage components that are part of the assembly. Simultaneously, as the thermal profile heats up the board, a fine balance needs to be maintained such that the board is hot enough to solder the components and yet, not too hot to burn the components, themselves. The reason is that -- due to board size and number of layers -- these thermal profiles are characterized by higher temperatures compared to regular commercial or industrial PCBs.
Fig. 3(a). shows a thermal profile for a regular eight-layer, 4 x 6-inch industrial PCB, while Fig. 3(b). shows a thermal profile for a 20-layer ATE PCB. Both PCBs use the same leaded solder paste. However, as shown, there are differences in ramp rate, soak time and time above liquidous (TAL).
Fig. 3(a). A thermal profile for a regular eight-layer, 4 x 6-inch industrial PCB (Click Here to see a larger image. Source: NexLogic Technologies)
Fig. 3(b). A thermal profile for a 20-layer ATE PCB. Both PCBs (in Figs 3(a) and 3(b)) use the same leaded solder paste. However, as shown, there are differences in ramp rate, soak time, and time above liquidous (TAL) (Click Here to see a larger image. Source: NexLogic Technologies)
Ramp rate is slightly faster for the ATE PCB thermal profile since the first three zones are set higher than normal due to the ATE PCB's size and thickness. Soak times for the ATE PCB are also different since takes longer to provide sufficient time for paste to melt prior to reflow. Also, TAL is longer for the ATE PCB than a regular PCB to achieve optimal solder spread on the solder joints across the large and thicker ATE PCB.
Before we get ahead of ourselves, let's back up a bit. To get to that perfect thermal profile, you need a solder sample from the OEM customer. All types of PCBs require a solder sample to create a thermal profile. However, when it comes to an ATE PCB, that solder sample takes on new meaning because it takes a longer time to create that perfect thermal profile for a big ATE board that has many layers and planes.
For regular industrial boards, a profile could possibly be created from experience and knowledge. But process engineers don't want to take a chance with ATE boards, so they prefer to create an ideal profile using a solder sample.
A solder sample is a non-usable PCB the OEM customer provides to the electronics manufacturing services (EMS) provider for the purpose of performing experiments, taking mechanical dimensions, and then creating a thermal profile.
The solder sample allows a number of testing experiments; among them, running the sample through the reflow oven to create the perfect thermal profile. The point is that you don't want to run an actual ATE PCB through multiple heat cycles and risk damaging it as you develop the thermal profile.
Once the ATE PCB thermal profile is perfect, it's then set up on the reflow oven to run the live product. The board may go through reflow two times in case some of its components need rework.
A proper stencil is used to precisely dispense solder paste onto components on an ATE board. At first glance, inexperienced ATE PCB assembly companies may view such a stencil design as merely another simple step in the assembly process with little or no extra effort put into it. It's just the opposite. Correct, precise stencil design is the linchpin of an ATE board assembly, and thus is extremely important.
Let's take a small radio frequency (RF) surface mount (SMT) component. Stencil apertures must be accurately designed so that the stencil can accommodate the component. Knowing and understanding stencil aperture patterns and how they affect solder reflow behavior are especially important; however, they are often ignored. When that, and other, factors occur, considerable rework is the result. In short, omitting key steps in an ATE board stencil design defeats the whole purpose of placing an ATE board on an automated assembly.
The assembly process can incur adverse effects when the stencil is not accurately designed. There can be such flaws as a number of tombstones and bridging when an incorrect stencil is run through the pick-and-place and reflow process. Fig. 4. shows an example of tombstoning. Tombstones refer to components that are lifted on one side.
Fig. 4. Tombstones are lifted components from one side. This flaw could be due to inaccurate stencil design, among other factors (Click Here to see a larger image. Source: NexLogic Technologies)
This flaw could be due to inaccurate stencil design, among other factors. This results in costly and time-consuming amounts of touch-up and re-work after the assembly is completed. For the ATE PCB customer, this extra work translates into delayed delivery shipment, cost increases, and considerable (but unnecessary) stress being placed on the board's existing components. Designing and implementing the right stencil can eliminate all these extra problematic areas.
Avoid DUT Compromises
The device-under-test (DUT) site (or sites) is the most critical part of an ATE PCB. This is where a component or chip is placed for testing. There can be one or more DUTs on a board; e.g., the four DUTs shown in Fig. 5. Others can be a dual-site board with two DUTs where a microprocessor (µP) or central processing unit (CPU) is to be placed for testing.
Fig. 5. ATE PCBs must be comprehensively cleaned because they have a unique section called the DUT or device-under test site where a component is placed for testing. Minute residue on the DUT can adversely affect chip or component testing (Click Here to see a larger image. Source: NexLogic Technologies)
If the DUT is compromised in any way, the ATE PCB becomes useless. Hence, details are of the utmost importance. For example, nut fasteners, referred to as PEM nuts (brand name Penn Engineering & Manufacturing Corp.) are used to keep the DUT socket in place. If these are not properly installed, the DUT socket is not correctly attached. As a result, the chip or component to be tested cannot be loaded onto, or tested on, the DUT.
Further, protecting the DUT during board assembly can pose issues. In this instance, Kapton tape used to protect PCBs during reflow often leaves small residues. This can pose a problem since DUT pads are highly sensitive to any residues and contaminations. Here, so-called Pogo or contact pins are applied for board contact instead of conventional soldering. This solder-less pin contact is highly critical, meaning the DUT and tester pads must remain pristine clean during assembly. Protecting those key areas from any contamination demands special attention during assembly.
Proper cleaning comes into the picture at this point. The main reason ATE PCBs must be properly and comprehensively cleaned is largely due to the DUT.
DUTs must be treated with extreme care. For example, a tiny piece of solder in the DUT area can be cleaned and it may appear OK cosmetically. In some cases, however, at the extremely high-speed levels of testing, the DUT may not perform the way it's intended.
Specifically, let's say the board is designed for 10 gigahertz (GHz) speeds. It's running at peak. However, residue flux or minute contamination remains on the high-speed running traces. That residue is cleaned, but trace degradation results due to the cleaning process. That trace is such that when testing takes place, the speed being tested may or may not go over 8 to 9 GHz and may not even reach all the way to 10 GHz.
Additionally, special care must be applied to eliminate any type of debris, foreign body, fingerprints, hand notions, body perspiration, and other forms of contamination from getting on an ATE board before it goes into the reflow oven. For example, a permanent fingerprint, Fig. 6, may jeopardize the high-speed integrity of the board.
Fig. 6. A permanent fingerprint left on the PCB's surface may jeopardize the high-speed integrity of that test board (Source: NexLogic Technologies)
The emphasis is on extreme care. Aqueous cleaning is in demand here. This means going beyond de-ionized (DI) water and using batch cleaning with chemicals used in a certain way to assure ATE boards are extremely clean. All the residues are cleaned off the boards because of these special cleaning chemical agents.
So, as we see, the assembly of an ATE PCB takes on a completely different mindset than that of a conventional PCB. It's not only maintaining a high-level of ATE PCB expertise in the front office, but also placing special attention on several key assembly practices and procedures. This includes having a good handle on the correct thermal profiles, paying close attention to items relevant to ATE PCB assembly such as PEM nut installation, as well as a precise stencil design, and assuring ultra-clean surfaces, especially for the DUT.
Zulki Khan is the Founder and President of NexLogic Technologies, Inc., San Jose, CA, an ISO 9001:2008 Certified Company, ISO 13485 certified for medical electronics, and a RoHS compliant EMS provider. Prior to NexLogic, Zulki was General Manager for Imagineering, Inc., Schaumburg, IL. He has also worked on high-speed PCB designs with signal integrity analysis. Zulki holds a B.S.E.E from N.E.D University and an M.B.A from the University of Iowa. He is a frequent author of contributed articles to EMS industry publications.