Reducing the risk of malfunctions that could ultimately lead to the physical harm of road users is a huge challenge. That's why many of the auto makers turn to formal verification.
The automotive industry is undergoing a period of rapid and disruptive transformations. Apparently, self-driving cars will be ready for urban ride-sharing fleets and equipped with no steering wheel or pedals by 2021. Vehicle-to-everything connectivity, autonomous driving, a new generation of human-machine interfaces and new industry players will bring a level of unprecedented creativity and innovation.
Innovation brings on new challenges. Chip verification design engineers of automotive and other mission-critical applications are facing two fresh challenges –– safety and security. The New York Times recently reported that security experts are in high demand with automobile manufacturers to help tackle cybersecurity threats. Security experts have it covered!
Safety is as important. Reducing the risk of malfunctions that could ultimately lead to the physical harm of road users is a huge challenge. That’s why many of the auto makers turn to formal verification. Formal verification has it covered!
Formal verification is a valuable verification tool for any hardware application, though its ability to debug automotive and mission-critical applications may prove to be its most effective use to date. As complexity grows and engineers analyze the behavior of their designs under a wider range of workloads, including malicious inputs, formal verification is employed to develop safety-critical hardware and an increasingly wide range of tasks. It ensures that suppliers of mission-critical applications, especially automotive electronics, meet rigorous ISO 26262 and other international safety critical standards that govern the development of safety-related electrical and/or electronic systems within road vehicles.
ISO 26262 specifies two types of component faults that must be fully verified. Systematic faults are introduced during component development, either through human error or tool or methodology malfunction. They are handled by rigorous verification and carefully tracking specific device requirements. The standard also addresses random faults that occur during the actual operation of the device due to external effects. These faults must be safely handled by the device’s circuitry that requires the use of fault-handling capabilities built into the systems and verified to ensure that they will catch the vast majority of possible random faults.
Two serious considerations for chip design verification engineers and where formal verification has it covered!
Formal verification captures specification elements in verification tests, and then accurately measures and feeds back coverage to systematically close the verification. Several formal verification suppliers have driven in to provide comprehensive safety critical analysis and diagnostic coverage solutions for automotive and other mission-critical applications. Their tools handle both systematic and random fault verification with improved ease-of-use and capacity advances to make them powerful techniques to uncover hardware design bugs that might otherwise escape simulation-based verification and lead to systematic failures. Formal verification can examine design behavior exhaustively without the need for input stimuli, and proves that the design never deviates from its intended function, as specified by a property or assertion, something simulation tools cannot achieve.
ISO 26262 specifies that requirements must be individually tested and this testing process carefully tracked. Formal verification has that covered!
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Security experts weigh in on cybersecurity threats and have it covered. As auto makers have found, formal verification tools provide significant value for the efficient development of automotive and mission-critical hardware. For safety, formal verification has it covered!
The New York Times articles from the Bits Section, include:
-- Dave Kelf is vice president of marketing at OneSpin Solutions. Previously, he was president and CEO of Sigmatix, Inc. He worked in sales and marketing at Cadence Design Systems, and was responsible for the Verilog and VHDL verification product line. As vice president of marketing at Co-Design Automation and then Synopsys, Kelf oversaw the successful introduction and growth of the SystemVerilog language, before running marketing for Novas Software, which became Springsoft (now Synopsys).