As FPGA-based realizations become bigger and more complex, synthesis tools that deliver an automated flow are the obvious choice for creating optimized designs in a timely manner.
The market is changing for FPGAs due to advancements in low power, high performance, and lower cost, all of which are increasing FPGA adoption into datacenter applications like network switches, CPUs, and network acceleration.
The growing need for FPGAs in these types of applications is being driven by the fact that they can achieve the desired processing throughput and latency requirements. With increasing amounts of data to process from very large data sets, FPGAs are a good fit to handle the acceleration required by these types of applications. While the flexibility of FPGAs is an advantage for FPGA designers, it also poses challenges in that -- in addition to the hardware -- the designers must implement the drivers, software, and application layers for these applications. Furthermore, they will need to achieve the best quality of results (QoR) for performance and area, accelerated runtimes, and deep debug to help accelerate system design and get to the market quickly.
There is increasing pressure to complete products in less time and with fewer resources. Accelerating time to market maximizes the opportunity for product revenue. Even after a platform is completed, there is an additional need to leverage the reprogrammable nature of FPGAs to continuously update functionality and fix issues for many years. To keep up with design iterations once deployed, designers require tightly integrated FPGA synthesis and debug tools to integrate fixes faster and to tune the design for optimal performance using an incremental compile technique.
For applications that are even more performance and process intensive, like machine learning, artificial intelligence, and image recognition using Convolution Neural Networks (CNNs), FPGAs also offer a distinct advantage through their ability to implement computational and data path operations in a massively parallel fashion. The inherent parallelism of FPGAs provides an opportunity to achieve very high data processing bandwidths, but also creates a challenge for FPGA designers in that they need to strike the right balance between highest performance and smallest area.
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Traditionally, this is achieved through the capturing of correct and high-quality constraints. However, due to the large size and complexity of today's high-end devices, this is no longer good enough. Now, designers need to utilize physically-aware synthesis and intelligently apply settings to the backend place-and-route tools to better meet timing and eliminate iterations. Here again, a robust synthesis tool that automates the FPGA design flow is a requirement, as it will ensure that designers achieve the highest QoR. Additional techniques, such as distributed synthesis, are also a big help with very large designs since reducing runtimes is critical.
Smaller, faster, and quicker design utilizing Synplify Premier (Source: Synopsys)
FPGAs are attractive for communication and datacenter applications as they enable a significant gain in processing bandwidth, the ability to complete in-system updates, and the opportunity to consolidate multiple sub-systems and controllers into a single device. The combined result is reduced cost and risk for FPGA designers and reduced power for the designs. As FPGA-based realizations become bigger and more complex, synthesis tools that deliver an automated flow are the obvious choice for creating optimized designs in a timely manner.