Session 10 is focused on ReRAM with papers scheduled from IMEC on hafnium-oxide ReRAM and on a self-rectifying, vacancy-modulated ReRAM cell with potential for use in a vertically stacked 3D-ReRAM memory at around the 10 nm minimum geometry.
These two papers are due to be followed by one from authors at foundry Taiwan Semiconductor Manufacturing Co. Ltd. Paper 10.3 is on a tantalum oxynitride (TaON) memory cell that can be included within a 3D via and that is compatible with the foundry's 28 nm HKMG CMOS logic process.
The memory is a TaON resistive film deposited as a cross-point memory cell between a copper via top electrode and a copper metal bottom electrode laid down as part of the conventional copper damascene process. According to the abstract, the unit area is four times that of the minimum via size in 28 nm CMOS design rules. However, the ReRAM is simple to manufacture and shows good scalability and compatibility with the native process, according to the authors. They claim it would make a low-cost, high-density, embedded NVM option for advanced CMOS logic.
The paper is due to be presented one year after a similar one was presented by research team from Taiwan's National Tsing-Hua University suggesting that a strand of what was academic research has moved a step closer toward commercial realization. (See: Taiwan embeds ReRAM in 28-nm process.)
The TSMC embedded ReRAM paper is followed by one from National Chiao Tung University and National Nano Device Laboratories in Taiwan on a 3D-ReRAM based on a tantalum-oxide/titanium-oxide bilayer. This Ta/TaO/TiO/Ti interfacial switching device overcomes the intrinsic tradeoff between operating current and variability in filamentary ReRAMs and shows potential for high-density data storage. But it is also notable that two of the authors are from Winbond Electronics. (See: Winbond at a Crossroads.)
Another branch of the resistive memory family tree will also be represented at IEDM 2013. In Session 30, in an invited paper from Adesto Technologies, a version of Adesto's conductive bridging memory (CBRAM) is presented that offers "excellent" retention at temperatures up to 200 degrees C. In the abstract for the following paper, authors from CEA/Leti in Grenoble and Altis Semiconductor admit there is a severe issue around the variability of the high-resistance state and the retention at high temperature that is limiting industrialization.
In the paper, the authors intend to present an experimental and theoretical analysis of a CBRAM that scales down to 10 nm based on Al2O3/CuTeGe. One conclusion of the paper is that the filament shape significantly affects the memory stability at high temperatures.
The memory research environment is extremely rich at present, and this is reflected in the IEDM program. Besides memory, there will be papers on digital logic, on analog circuits, MEMS sensors, and displays, as well as on circuits and processes for emerging technologies such as biosensors, bioMEMS, energy harvesting, power devices, magnetics, and spintronics in a program that will include 215 presentations in 33 sessions.