Now we are ready to bring all the parts together and construct the GPS-driven, FPGA-decoded Nixie tube speedometer for use in a 1953 International pickup truck.
Driving the Nixies
Each Nixie tube will have at most one digit turned on at any particular time. The tubes sink 2ma and require approximately 160V. The anode is driven by the high voltage, and the FPGA will pull it low to close the circuit. I purchased a simple DC-DC converter to generate the high voltage. To reduce the input/output count in the FPGA, I purchased two K155ID1 chips. To keep the current at 2mA, we need a ~10kΩ resistor in series on the anode side. The K155ID1 chips are specifically designed for Nixie tubes. They have a BCD input and a 10-digit output. Below is the pinout diagram for these chips.
Remembering that the Nixie tubes came from a Russian source, their pinout chart seems so Cold Warish and makes me want to yell, "Tear down this wall!" Anyway, in the case of my tubes, we are interested in the HH-12B pinout on the right-hand side, as illustrated below.
All you have to do is turn the tube over and find the arrow symbol, which is the anode (+) 160V side. Going clockwise, pin 2 is digit 0. Pin 3 is digit 9. Then we have digits 8, 7, 6, ..., 1.
Driving a single digit in the Nixie tube is easy. Just wire the anode up to the + high voltage and the cathode of the digit you wish to light to the ground.
Driving the seven-segment LED displays
As illustrated below, the seven-segment LED displays on my FPGA board are multiplexed, which reduces the I/O count for the FPGA. Possibly we could have done something similar with the Nixie tubes, but maybe the strike factor time for a Nixie would have prevented that.
The idea here is persistence of vision. Some displays change so fast that your eye and brain will merge the images. If we light the first seven-segment LED digit for 1/10th of a second, and then we do the same for the second, the third, and the fourth, it will appear to the observer as a single display in which each digit is constantly illuminated. In addition to reducing the number of FPGA pins, this lowers power consumption, thereby making everybody happy.
Of course, the data feeding the display cannot change faster than four times the sample rate, or digits will change in midstream. I made my refresh rate around 600µs. This number is not critical -- it just has to be fast enough.
Following our exploration, now it's time to pull everything together...
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