The NAND flash controller in an SSD or PCIe card has two roles. It's responsible for managing the flash (read, write, recycle), and it interfaces with the user to handle requests for the flash. (Source: NAIT on Flickr)
Really enjoyed the blend of humor/technical content on this one. Anyone have any learnings to share on this:
"Choosing the wrong technology can eliminate the many advantages of flash. This is frequently seen when multiple SSDs are put in a standard disk drive shelf, where the SAS link to the server is filled by the input/output per second (IOPs) of two or three SSDs, so 90% of the potential performance in the shelf is never available."
In a NAND Functional Tester I implemented the algorithm to detect during Read/Verify the actual ECC required per Block and Device.
Applying repeatedly Erase/Program/Read/Verify cycles to the same block emphasized the Endurance (measured in number of Erase/Program cycles) based on the evolution of ECC detected during Read/Verify.
Lately a customer ran, on an ONFI2.2 Chip with ECC Unit of 1117 Bytes and minimum required ECC 40 according to the spec, repeatedly, Erase/Program/Read/Verify cycles on the same Block. During the first cycle the ECC detected by the tester for that Block was 6, after 3K cycles ECC detected was 17, after 5K cycles ECC 29.