No. 4: Wear leveling and error correction
Wear leveling and error correction are two things that vendors love.
(Source: Crispin Semmens)
There are a million ways to handle wear leveling, and almost all of them work. For error correction, you will often hear "up to N bits of error correction per 4 KB of data," where N is some big number. They won't point out that "up to" is not the same as "at least," or that non-errored reads are very different from failed read attempts. For consumer SSDs, the critical number is the failure rate of the SSD itself. For enterprise storage, the critical number is the mean time to data loss.
No. 5: SLC vs. MLC vs. eMLC vs. TLC
Though they are used differently, SLC, MLC, and eMLC are generally made from identical silicon parts. Only TLC parts are physically different.
(Source: Creative Commons)
Single-level cell (SLC) technology is like writing on wide-ruled paper with a sharp pencil. It's easy to write fast, read, and erase. Multilevel cell (MLC) is like writing on college-ruled paper with a dull pencil. It's hard to write fast and not very easy to erase. Enterprise multilevel cell (eMLC) is like writing on college-ruled paper with a mechanical pencil and reading the results with reading glasses. It's even harder to write fast, but it's much easier to read and erase. Using triple-level cell (TLC) is slow and error prone, and it has such a short endurance.
No. 6: 3D NAND
All that stuff about NAND becoming so small it won't work is about to change; 2D NAND cells have gotten so small that one can talk about counting the individual electrons they contain, with the resulting problems of slow programing, short life, and high error rates.
(Source: Omar Barcena and John Picken on Flickr)
3D NAND doesn't double the capacity of a 20nm 2D NAND by stacking two layers of 20nm NAND, but by stacking 16 layers of 40nm NAND, providing high endurance and low error rates. One of the most interesting things about 3D NAND is how differently various vendors have approached this new technology.
No. 7: Parallelization (processing and storage access)
NAND chip performance has improved and continues to improve, not because NAND cells have gotten faster, but because
of infrastructure improvements.
(Source: Violin Memory)
The speed limit on the roadway (the I/O bus) is 10 times what it was a few years ago. The number of bits read or written in a single operation has gone up from 4 KB to 8 KB to 16 KB. The number of write operations performed at the same time on a die has gone from one to two or four. Even without any changes in the NAND cell itself, NAND performance continues to increase as a result of greater parallel access and parallel operations.