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Showtime for the Micron-Sony 16Gb ReRAM
3/4/2014

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Figure 2. The basic architecture of the 16Gb Micron-Sony ReRAM.
Figure 2. The basic architecture of the 16Gb Micron-Sony ReRAM.

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Ron Neale
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Re: Development state vs PRAM
Ron Neale   6/22/2014 1:16:21 PM
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I am aware of the Panasonic MN101L which I think was the first embedded ReRAM in the field, I am not sure which ReRAM material they are using. I have not investigated the Philips product. It is the market and designers who will decide and when we see commercial products with them in then we can measure the success.

With respect to TiO2, I think in any device where you build up a concentration gradient of material that can be moved by electrical means relatively easily is likely to suffer from thermal degradation. I am afraid it's a case of dammed if you do dammed if you don't. If you require a high temperature/high energy to write the memory then that's a problem in many other respects, if you have low energy then diffusion might be the elevated temperature data retention problem.

Cost of ReRAM plant at 10-20nm Samsung should know, most of it will be for silicon processing anyway.

shockley22
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Re: Development state vs PRAM
shockley22   6/22/2014 11:32:29 AM
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Thanks Ron.

What is your opinion on the significance of the tiny Philips embedded RRAM that is the first commercial product in the class? 

Is the HP TiO2 device too "hot" to succeed, i.e., will thermal problems bedevil it same as PRAM?

I saw Samsung say somewhere it would cost $10B to build a fab that could manufacture their type of RRAM. Did you see that?

Ron Neale
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Re: Development state vs PRAM
Ron Neale   6/22/2014 11:20:37 AM
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Shockley 22:- You can never say phase change memory (PCM) is definitely dead, it is alive but at the moment to use a medical acronym more in the DNR phase. There are still a very large number of problems to solve if PCM memory arrays with chip bit densities that are competitive with Flash (say double digit Gb) and with cell sizes in the 10nm to 20nm lithographic range are to appear in the market place. Problems like elevated temperature data retention, element separation, current density, parameter drift, matrix isolation devices and thermal crosstalk, the latter two are very significant if you want to construct a three dimensional, or stacked matrix.

Part of the answer to your question regarding PCM may be found in the reason why now there are so many many different types of RRAM/.ReRAM memory mechanisms, technologies  and devices all competing for NV memory top spot. That effort tells you those workers believe there is still an opportunity and PCM has failed. I think there is still a lot of work ahead before something in the form of a competitive product pops out from the wide spectrum of RRAM/ReRAM opportunities. Of the RRAMs the one that interests me the most at the moment is the CeRAM (Correlated electron RAM). If all the performance and fabrication claims for this device can be established by independent third parties then it has to be the favourite to suceed and as a bulk effect it should scale. If Micron/Sony can turn their 16Gb RRAM copper filament based memory cell into a product in short order then (see my EETimes article) they might be onto a winner of sorts. However, I see that device more as a test vehicle for many different types of RRAM technology and should receive support for that reason alone to allow a quick jump from the laboratory claims to high end lithography.

I think as I said in my recent VLSI report in EETimes perhaps the ReRAM/RRAM community would be better served if they focussed their efforts towards on chip embedded memory and from success there build the bit capacity upwards.

shockley22
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Development state vs PRAM
shockley22   6/22/2014 10:01:23 AM
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Ron, thanks for the article. What is your evaluation now of the relative states of development for ReRAM and PRAM? Is PRAM to be forgotten? Is ReRAM an evolutionary advancement?

Shockley

resistion
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Re: 2nd ISSCC case
resistion   3/5/2014 9:11:24 AM
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It's a rather common spec, 105 cycles, 10 yrs (what temperature?)

http://www.flashmemorysummit.com/English/Collaterals/Proceedings/2012/20120822_S203C_Tsutusui.pdf

Ron Neale
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Re: 2nd ISSCC case
Ron Neale   3/5/2014 8:22:30 AM
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Resistion:- On 16Gb reliability nothing was provided in the ISSCC 2014 paper. However, in August 2012 at the Flash Memory Summit, Santa Clara, Amigo (Keiichi) Tsutsui of the Sony Corporation under the heading "Adaptive ReRAM Tecchnology for 2014" presented the results for a 10Gbit memory using the same CuTe copper filament bridge mechanism, with the same 1GB/s read and 200MB/s program performance as the ISSCC device. For that device a program endurance of greater than105 cycles was claimed with data retention of greater than 105 years. I am afraid that rather meagre bit of what might pass as "reliability" data is the best I can offer at the moment; with the caveat that results do not always necessarily transfer between different device structures.

On the subject of verify one important aspect of reliability involves the way in which, with the 16Gb ISSCC device, iterative set is used in relation to the CSP to reduce power. If with write/erase lifetime the number of tries required increases then it would appear to be the power dissipation budget gets compromised.

resistion
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Re: 2nd ISSCC case
resistion   3/5/2014 6:37:56 AM
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The reliability data still needs to be presented as well as the writing conditions. Actually, I see in the paper they have verify included.

Ron Neale
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Re: 2nd ISSCC case
Ron Neale   3/5/2014 4:38:09 AM
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Krisi & resition:-I requested from Micron the details of the power dissipation when the chip is operating at its maximum claimed read and write performance to complete my report. So far I have not received any reply. I think with that information it would be a little easier to judge how near the 16Gb device might be to product status or commercial availibility and higher bit densities-only Micron/Sony can really answer that question.

I think what is very important is Micron/Sony with the 16Gb GeCu-Cu bridge device now have a test structure and mask set that should allow other bi-directional NV memory technologies to be quickly evaluated at high bit density. In that role it will help solve the problem of getting laboratory claims for the performance of single or a few NV memory devices, from where ever they come, evaluated at high bit density and any problems in that respect quickly exposed.

krisi
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Re: 2nd ISSCC case
krisi   3/4/2014 10:55:26 PM
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is this IC commercially available? any prospects for 64Gb ReRAM?

resistion
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2nd ISSCC case
resistion   3/4/2014 10:05:46 PM
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Thanks for your breakdown of this paper.

It seems a little more transparent than the earlier 32 Gb chip from SanDisk/Toshiba.

The voltage was somewhat higher than I expected.

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