Don't confuse surge protection with ESD protection when specifying circuit protection. ESD occurs much faster.
I then explain that the X value he's holding on to originated from an 8x20 µs surge waveform that has very little relationship to the ESD waveform. What's more, with regard to ESD threats, there is debate on how to measure and specify the clamping voltage. Should we measure ESD clamping at the initial spike (1 ns), or should we measure this clamping voltage after the ringing has stabilized (30 ns)? (The figure below shows the peaks of current in an ESD waveform.)
The standard voltage-discharge waveform of an ESD event is an initial peak at 1 ns and a secondary peak at 30 ns. Because of the short duration of the initial pulse, ESD protection circuits need not be rated for the the full peak voltage (click here to enlarge).
Most ESD protection device datasheets ignore the voltage spike of the first peak. Instead, only the ESD clamping voltage at 30 ns is shown. I understand why this is done; the first peak is highly dependent on the test setup. Still, it's unfortunate that no reference is provided. This initial spike does matter. The first peak can be destructive, and we have plenty of anecdotal experience with the latest-generation ICs. In fact, when an ESD spike causes an oxide punch-through failure on the silicon IC transceiver, it's very likely that this damage resulted from this first peak. That says nothing of the radiated effects of ESD or the high frequency content in the first spike.
But just so we are comparing apples to apples, I also show the clamping at 30 ns, where the ringing and high-frequency components have settled out. At 30 ns, the device I have recommended is 30% lower than the competitor's device.
The 70 V that looked so daunting at the beginning of our conversation is actually a fairly low clamping voltage for the first nanosecond. After all, if I look at similar devices on the market, I could very well find clamping north of 300 V. (Again, this is very dependent on the test setup.) But it brings us back to the real question that hasn't been answered yet: Is the clamping voltage low enough to safeguard the IC transceiver driving his interface? The answer, of course, depends on the sensitivity of the transceiver, the severity of the transient threat, and the quality of the PCB layout. The way to verify this is to test the TVS device in the system.
In the meantime, if my friend needs more convincing, perhaps there is one more measurement technique that can predict whether I have given him a good TVS solution. Come to think of it, that seems like a very good topic for next time.
What's your experience with selecting ESD protection devices?