The move to 20nm bulk CMOS and 16/14nm FinFETs brings one of the most serious challenges the semiconductor industry has faced in 20 years.
The semiconductor industry has four main options to reduce cost per gate and cost per transistor as it scales to future nodes.
Adopt new device structures
One option (which I will cover in a future article) is fully depleted silicon-on-insulator (FD SOI). It gives lower cost per gate and lower leakage than bulk CMOS and FinFETs.
Use 450mm wafers
A key challenge with 450mm is determining which technology node is best suited for the transition. One probable scenario is that 450mm will be adopted at the 10nm and 7nm technology nodes. However, it is not appropriate to adopt extreme ultraviolet lithography and 450mm at the same technology node. That fact complicates the issue.
A 450mm wafer fab that can make 40,000 wafers/month at 7nm will cost $12 billion to $14 billion and will need to be ramped into high volume within a short time. Otherwise, depreciation costs can result in large losses. Such a fab will need to make products that can ramp to high volume rapidly.
There are efforts to address these challenges, but only a small number of companies are committed to this effort globally. Indications are that 450mm wafers will be in high-volume production at multiple vendors after 2020.
Strengthen physical design and design-for-manufacturing capabilities
A complex design in 16/14nm FinFET can cost $400 million or more. Spending another $100 million or $200 million to improve parametric yield means only a small number of applications can be addressed, because product revenue must be 10 times design costs. In addition, designs need to be completed in 12 months in order to support fast-moving markets such as smartphones.
Use software programmability based on embedding multiple processor cores
Programmable structures are expected to be increasingly adopted, but embedded FPGA cores have high power consumption and high costs. Software customization requires a relatively long time for developing and debugging complex tasks. Software development tools need to be enhanced, but the rate of progress is low.
I welcome input from readers, particularly on what they view as alternatives to the cost challenges of FinFETs. In my next article, I'll go into more detail on FD SOI.
-- Handel Jones is chairman and CEO of International Business Strategies Inc.