Jammy counts the move to 3D device architectures as one of the top drivers for both logic and memory, with new materials coming in second. What exactly will happen at 5 nm and beyond is not clear, but Jammy takes a realistic approach. "If you apply standard economically driven approaches to what scaling might look like at that point, the first thing we recognize is that the purpose of scaling is to add more functionality on a chip."
So whether the functionality is achieved through dimensional scaling or some other form of scaling, it's still scaling. "For a long time, the ITRS and others have proposed that functionality scaling can come from adding more analog, RF, and other 'More than Moore' components, or by system-in-a-package 3D/2.5D approaches," he said.
Increasing device density and functionality while driving down power may require the industry to think about how to apply the strengths associated with 3D device architectures to new technologies. "At 5 nm, we may have nanowire devices, and going beyond that, perhaps we just need to stack these devices in a fashion not very different from what is happening with memory technologies today."
The two researchers, along with representatives from Imec, Soitec, Sematech, Globalfoundries, and Stanford, will present on the topic of getting to 5 nm devices at the Semiconductor Technology Symposium at Semicon West.
-- Debra Vogler is a strategy adviser for SEMI, the trade group that hosts Semicon West.