Embedded DRAM's process integration designed to facilitate further scaling
The Intel eDRAM embedded in the Intel GT3e graphics processing unit, and used by the Haswell G82494 processor, was fabricated using nine levels of metallization with 22 nm Tri-Gate transistor technologies. The Intel eDRAM die, in GT3e GPU, also used the manufacturing proven multi-layer replacement metal gate process seen in their Ivy Bridge device. Silicon source/drain regions were used for the NMOS transistors and SiGe for the PMOS transistors. The embedded DRAM cell was 0.029µm2 large. The cell capacitors were formed in trenches patterned through the ILD dielectrics supporting the metal 3 and metal 4 interconnects. Gate last high-k metal gate (HKMG) finFET transistors were used for the eDRAM access transistors having a 107 nm wordline pitch. Figure 2 depicts a general overview of the embedded DRAM. The capacitor trench bottoms were supported by the via 1 and metal 2 Ta-based barrier layer.
Figure 2: Middle of the array (TEM cross section through the storage node contacts in bitline direction, parallel to the fins), Intel eDRAM die in GT3e GPU. Click here for larger image.
The Intel eDRAM device used a twin-well process for the eDRAM array access transistors. The device did not appear to use an embedded well process, as the transistor's channel was decoupled from the substrate, yielding threshold voltages that were independent of well bias. FinFETS transistors have a limitation that they have a quantized width so gate widths were increased by adding fins in parallel to the transistor. Intel employed a finer pitch for peripheral logic and more relaxed pitch for the NMOS access transistors in the eDRAM region. A relaxed pattern was used in eDRAM region to give low Ioff leakage currents in DRAM access transistors.
Figure 3 compares the pitch of the fins in the periphery and in the memory area. The cross-section is taken perpendicular to the fins, parallel to the wordline. The minimum pitch of fins are shown in the periphery and in the array and in both cases, the STI was covered by metal gate.
Figure 3: Comparing the Fin Pitch in the periphery and in the memory array. (TEM cross section in perpendicular direction to the fins, wordline direction), Intel eDRAM die in GT3e GPU. Click here for larger image.
The single fins for the peripheral NMOS transistor and the eDRAM NMOS fin based access transistors had different dimensions. The fins in the periphery had larger radii of curvatures to achieve greater channel lengths. This was the first Intel device to incorporate an eDRAM and it was probably a test vehicle as preparation for its next generation processes. The DRAM cell area was 0.029 um2, with a wordline pitch of 107nm and these measurements suggested a 5x nm process node, which was midway between the conventional 59nm to 50nm DRAM nodes. Hence, Intel eDRAM cell area was about three generations behind the peripheral logic.
The eDRAM cell layout had a relaxed 8F2 configuration, where F is defined as half of wordline pitch (107nm ÷2 ~ 54nm). The unit cell in a typical 8F2 DRAM was rectangular, the long side being 4F and the short side 2F. The Intel eDRAM being also rectangular is 4F wide in the bitline direction and 2.5F long in the wordline direction. This relaxed 5x nm node eDRAM had some very advanced features too. The active area was not continuous but consisted of isolated strips and the STI pitch was the same as the wordline pitch, which is not usually the case.
The Intel eDRAM die had its cell capacitors placed between the metal 2 and metal 4 interconnects. The etch stop layers between metal 2 and metal 4 were used as mechanical supports to hold the capacitors in place. The capacitors were half the size of regular standalone DRAMs. Figure 4 shows a TEM picture of the capacitor and its dielectrics. The dielectric material consists of ZrO and is sandwiched between TiN layers that act as electrodes.
Figure 4: TEM cross-section showing the capacitor dielectric of the Intel eDRAM die in GT3e GPU. Click here for larger image.