Cisco's entry to the CMOS photonics market is its small IEEE-compliant 100G-LR4 pluggable transceiver module (CPAK) that's less than a third the size and power of the current generation pluggable module (CFP) technology, making it possible to access more of the existing bandwidth available in the Cisco chassis while reducing power consumption.
"We wanted to use a commercially available technology that leverages a well established fabrication infrastructure," says Nowell, noting that CMOS allows high density integration of optical devices on silicon. He points particularly to the semiconductor industry's progress in technology for stacking different kinds of chips together with through-silicon vias or silicon interposers that now allows combining these components with high speed ASICs.
"The remaining challenge, however, is to leverage the high volume, low cost packaging expertise of CMOS for the optical industry, for a convergence of the two ecosystems," Nowell says, noting that this will mean a transition in the industry and likely a lot of new partnerships, to figure out the best way to address these new challenges.
"There are a lot of smart people in the packaging world, but you ask them how to do it at high volume and low cost with fiber attachments, and they scratch their heads," says Nowell. "Leveraging CMOS technology to break through the optics bottleneck provides many compelling benefits to both vendors and customers."
Intel has demonstrated a 100Gb/sec photonic chip at the 2013 Beijing IDF in April. Intel in a following interview, said they have engineering samples out now and are planning to go to market within the year.
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