Another approach taken by IBM and Macronix to address phase change memory drift was to find a means of the reducing the statistical spraed of the resistance levels of MLC
The second of the two joint IBM-Macronix PCM papers at VLSI 2015  presented an equally innovative new approach to the problem of a 2bit/cell MLC drift. In this case, not by matching the sensing levels to the variation in PCM cell characteristics as discussed earlier in Part 1.
The new and different approach was to find a means of reducing the statistical spread of the resistance levels of the MLC. This would mean in the presence of drift, the distributions would take much more time before the resistance values for different MLC data levels overlapped, resulting in a read failure.
There are two possible ways to obtain the middle two levels of the four levels of a 2bit/cell MLC. One is to SET a cell to its low resistance state and then progressively RESET it, using read verify to stop when the required resistance level is reached. Or, alternatively, RESET the cell then progressively SET the cell with a series of SET pulses again until the desired resistance level is reached. The IBM team elected to use an iterative SET/verify scheme to achieve the four resistance levels required for a 2bit/cell MLC.
The reason for this choice is the IBM authors discovered that for a 2bit/cell PCM the spread of the “10" logic state resistance was relatively small as a function of current, but the spread of the “01" data state resistance of a 2bit/cell always had a wider spread, irrespective of the means used to achieve it. They accounted for this by the observation that the broad spread occurs whenever the current levels are such that melting occurs during either SET or RESET; during RESET it always occurs. However, the SET step is not usually associated with melting as the crystallization temperatures are much lower than the melting temperature.
In the past there has been much debate about when and how much melting occurs during SET and the volume of material involved. The reasons why melting is required during SET was well exposed by the recent definitive work from IBM (Zurich) on crystal growth rates. That work established maximum crystal growth rate, the shortest SET time, occurred near the melting temperature. Figure 1 shows from temperature profile and the volume of molten material during SET at different current levels for in this case a 55nm size “dome" device. The small red arrows mark the molten interface as higher crystal growth rates are required.
Figure 1: (a) Examples of Temperature profiles and melting for different SET currents, (b) the possible profile for the I(melt) current.
The IBM/Macronix use of iterative SET and avoided melting by employing a SET current that resulted in a temperature profile without any molten material. This would result in a profile for their cells without the minimum molten plug, where the SET current would be called I(melt). Therefore the SET current for this latest work was always < I(melt) and of an actual value <50µA was determined for the particular PCM cell structure involved.
Figure 2: The converging resistance SET current profiles as a function of time for 4 level MLC SET without melting which minimize the statistical distribution.
In all cases, initially a single RESET pulse is used to fully RESET the cell. A pulse with a long stepped trailing edge is used to fully SET the cell for the “00" data state, a single RESET pulse is used for the "11" data state.
For the “10" data state a 160ns stepped trailing edge pulses each increasing in maximum amplitude to a value less than I(melt) are used. For the “01" data state stepped trailing edge pulses of the same amplitude
While the use of iterative SET without melting to determine the data state removed the wider statistical distribution of the “01" state relative to the “10" state, another benefit occurs that causes the resistances to converge and narrows the distribution even more.
The explanation of this benefit relates to the diameter of the “dome" after the initial RESET pulse; it has a wide variation in diameter and therefore resistance. This means the high resistance cells in the RESET state, the starting point, reach a higher temperature during SET and therefore the crystal growth rate is higher. While the lower resistance cells are heated to a lesser extent by the same SET current pulses, crystal and growth is slower. In both cases, this causes the resistance to converge to a narrower distribution.
The result is when drift occurs the tight distribution of the resistance of the “10"and “01" to not overlap with each other or the “00" or “11" states and compromise the stored data.
For SCM memory applications IBM this latest work adds to the options that can mixed and matched as potential solutions to the serious problems associated with drift and temperature in PCM MLCs.
↩ A Novel self Converging Write Scheme for 2bits/cell Phase Change M for Storage Class Memory (SCM) Application, by WC Chien et al, IBM/Macronix International, Proc VLSI2015.
↩IBM's First Novel PCM Fix, by Ron Neale, EE Times.
↩ Crystal growth within a phase change memory cell, by Abu Sebastian et al, Nature Communications, 5, article number 4314, July 2014.