Intel’s focus on transistor performance can be traced back to the height of the PC wars when the benchmark was clock speed. While Intel focused on transistor performance, the foundries adapted Intel’s transistor innovations for their own SoC integration needs. In addition, they aggressively pursued metal density scaling and cost reduction. While Intel pursued a limited vertical functional integration, the foundries developed a lateral ecosystem and designed transistors for a variety of vendors that independently optimized functionality for each IP block (CPU, GPU, radio, modem, GPS, etc.).
This vast ecosystem of existing design IP is now a significant influencer on the adoption of the next transistor architecture. Arguably, the foundries are today better positioned for the SoC era in spite of having a non-leading edge transistor. TSMC has stated that in 2012 it will integrate a variety of IP blocks and ship highly complex mobile SoC parts to its customers. These processors will be made in 28nm technology and will likely set new benchmarks for cost, power and connectivity features. As an example, the Snapdragon processor by Qualcomm might well become the most highly integrated SoC to debut Windows 8 in 2012. Intel has the clear advantage at the transistor level and will win the CPU space, but the ecosystem has the advantage at the system level and is poised to win the SoC space.
“Making it smaller doesn’t help anymore”
Geometric scaling of the transistor below a pitch of 80nm tests the limits of traditional lithography. Innovations like double/triple patterning and spacer layer transfer are needed to print features below that pitch. Extreme ultra-violet (EUV) patterning has been in development for close to a decade as the
successor to 193i patterning but remains costly with limited throughput and ROI.
Since the foundries are ahead of Intel in metal pitch scaling, they will be the first to hit the immersion lithography limit and be required to transition to novel patterning techniques or ultimately EUV patterning. Even then, the cumulative cost of patterning will be so high that cost-per-gate is expected to stay flat or even go up when scaling to the 20nm node. It is unlikely that foundries will be able to execute two radical changes (tri-gate and new patterning) within the traditional 2 year development cycle. The 28/20nm nodes will be very long lived as foundries grapple with increased cost and complexity in addition to traditional scaling challenges. This will be another inflection point in the morphing of the traditional Moore’s Law metric of cost-per-gate.
“Cost-per-goodness” replaces “cost-per-gate”
In the SoC era, as “cost-per-gate” plateaus, the new driver will be “cost-per-goodness”. Packing as many features (goodness) on a chip as possible at the lowest integrated system cost and power will win. However the cost to design that functionality is also increasing rapidly.
New 28nm chip designs cost as high as $200M compared to 45nm designs which cost <$100M. While the bulk of this increase is attributed to design complexity, mask costs and embedded software costs are also increasing significantly.
The transistor architecture that is most compatible with all the IP needs of a complex SoC at the lowest cost will thus have the upper hand. As technology development lifecycles get longer and product lifecycles get shorter, foundries will try to extract all the goodness in an existing transistor technology before moving to the next one.
[Part two of this article will discuss potential paradigm shifts in the SoC era. As scaling hits physical and economic limits, the industry will continue to innovate more than ever before, but that innovation will likely be centered on extending the life of an existing geometry, rather than be driven by scaling
the geometry itself.]
-- Pushkar Ranade is director of process integration at SuVolta, Inc. Prior to joining SuVolta in 2010, Ranade was with Intel Corporation where he contributed to transistor process integration and development of Intel’s 65nm, 45nm and 22nm logic technology. Ranade joined Intel in 2003 after graduating with a Ph.D. from the University of California, Berkeley. At Berkeley, his research was in the area of sub-70nm CMOS transistor design and involved the integration of novel gate materials and ultra-shallow junctions. The opinions expressed here are his alone,and do not reflect those of EE Times.
very well written, look fwd to reading part II, would be interested in the author's thoughts on how die stacking by 3D TSV will upset the current deadlock ( CPU by smaller transistors vs SoCs by ?? transistors ).
I agree that scaling is hitting physical and economic limits and that innovation will likely be centered on extending the life of an existing geometry. Yet, I would like to suggest that the more effective path to using existing manufacturing tools, process technology, transistor structure, etc. is to use monolithic 3D. NAND vendors are already going there and many should follow. The advantages of monolithic 3D are quite significant in device integration, power and performance, and will not need new transistor technology
I agree with you. From the typical usage model of end user, now they don't know why they need such a high performance CPU. The reason why they buy a PC is because PC helps them to get information from internet, play some casual game.
Before a new popular usage case is found, such as popular AI usage at home, cpu performance is engough. While the other factors, such as disk speed, wireless, power, cost, total system size, are the impact factor for the end user.
As internet development, people are much more earier to find the different architectur software, so architecture restriction becomes a less restricted factor.
As the future for human being is to collabration not to fight, so the SOC represents the internal desired spirit of human. Thus can bring more innovation and reduce cost.
Well written! The major rule for wafer fabs is Take no Risks--protect and preserve that huge capital investment so you can pay it down. Change gets equated to risk, especially for wafer fab managers and product developers. So, what’s least risky among the choices of continued scaling, new devices/architectures, 3DIC with TSV, or monolithic 3DIC? I try to parse the variables in a blog post: http://www.monolithic3d.com/2/post/2012/01/is-monolithic-3d-ic-less-risky-than-scaling-or-tsv.html
Hi Zvi, don't you think there needs to be a fundamental shift in IC vendors' business model -that with more progress in SoC and 3D IC's (monolithic & stacking), software is an important component of the offering? To that end, shouldn't the IC companies be working to provide application platforms for developers to spring-off of? I know some of them do but it is inadequate and certainly not accelerating the innovation we all like to see in 3D.
@Pushkar Ranade: great writeup! I hope you continue to post on EE Times.
Thanks all for the comments.
Today, on-chip integration is the ideal solution for cost, power, form factor and reliability. Die stacking and TSV are viable options to extend the life of CMOS once traditional scaling ends. A key pre-requisite for die-stacking is that total package thermal design power (TDP) needs to be low. Hence, the power dissipation of each die/layer needs to be minimized before they can be stacked – which is an even bigger issue for stacked die than for traditional monolithic solutions. Another consideration is price point of stacking compared to more on-chip integration.
I think this is all very interesting... clearly we have a growing problem in our ability to advance processor performance. However, I'm of the opinion that we can't overcome this with better transistors (at least not for long). We need a new architectural paradigm - the traditional approaches are fundamentally out-dated. My bet is on highly efficient, small massively paralleled manycores...