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3D Stacks Need Lower Costs, Broader Backing

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HBR1
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Re: Those who Know
HBR1   12/1/2013 5:05:52 PM
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Hi Gil, thanks for your input! I fully agree with your "Those who know don't say".

It reflects exactly what I see. Sorry, I have to be brief here, otherwise I may fall into the other category...Herb

HBR1
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Re: Why Intel is not backing
HBR1   12/1/2013 5:22:32 PM
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You are right! Intel is in the camp that wants to include memory management in their SoCs and processors, therefor prefer the HBM (high-bandwidth memory) concept.

I see both HMC (hybrid memory cube) supported by the 100+ member companies of the HMC Consortium, as well as HBM being used to add large amounts of memory close to processors, to break down the "Memory Wall" by significantly reducing latency and increasing bandwidth by a magnitude or more.  

By the way, JEDEC just published the HBM spec in a very detailed document. You can review or download it from their website.

Deails about the HMC are available from the HMC Consortium. 

BillM210
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3D Stacks vs ASIC
BillM210   12/1/2013 6:10:28 PM
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When ASICs first came out, many designs were quickly converted from PCB/TTL into single ASIC chips.    These were really not complex nor large designs.  As new silicon nodes were released, the doubling of gates quickly allowed large system on chip designs with cpu/dsp processors, lots of memory and control logic.  But by the time SoC's were developed, all had grown accustomed to the ASIC development flow. 

Many continue to talk about 3D Stacks which is a huge step function in business and technical complexities while it appears that many are overlooking the 2.5D/interposer as a very viable solution with significant benefits in area, power, performance, cost, etc.  Buidling confidence and success stories with 2.5D solutions (like Xilinx, Global Foundries/Open Silicon/Amkor, etc) might be the fastest method to accelerate 3D TSV. 

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