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rick merritt
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SOI users at 20nm?
rick merritt   4/7/2014 2:51:02 PM
In all this lively debate I have not heard of any SOI users beyond STM. Any others out there?

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Re: SOI users at 20nm?
Adele.Hars   4/7/2014 4:24:39 PM
Rick, try the FD-SOI Design Community on LinkedIn for more (not just ST) insight. The FDSOI crowd jumps from 28 to 14nm - not bothering w/20nm --altho Handel is a purist w/respect to nomenclature, it seems ;-) -- anyway, when he says 20nm, the FDSOI folks call it 14nm (that's what they're going head-to-head with, after all). Soitec also has good info - see latest ASN on Gen2FDSOI (28nm performance beats 20nm bulk (and costs 50% less); 14nm matches FinFET (at 20% lower cost). Also CMP has a been seeing good results in their MPW runs - they've got 140+ users of the 28nm FDSOI PDK (which granted, is provided by ST/Leti) -- hear they're pretty pleased with the results they're seeing.

SOI lady
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Re: SOI users at 20nm?
SOI lady   4/8/2014 10:21:43 AM
And be patient... STMicroelectronics will soon be announcing a "major foundry player" that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry.  This important piece of news came out of the company's Q4 and FY13 presentation in Paris on January 28th.... 

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Re: SOI users at 20nm?
krisi   4/8/2014 10:26:49 AM
any leaks what the announcement might be @SOI lady?

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Re: STM micro bias
JeffL_2   4/8/2014 12:15:24 PM
"All the industry is going to FinFet, following Intel that has a three years lead and experience"...

Oh sure, I mean Intel has a PERFECT record on process selection, they've NEVER jumped on a technology before it was "ready for prime time" and regretted the consequences, have they? Oh and by the way has anybody seen my bubble memory USB key, I think I must have misplaced it somewhere...hmm!?

Austin Tech Watcher
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Re: SOI users at 20nm?
Austin Tech Watcher   4/8/2014 4:29:51 PM
IBM uses SOI for its Power processors. Your point is valid: Freescale stopped using SOI because of gaps in the design IP, and AMD also retreated. It is hard to gain back the cost of the wafer for $20 chips, I was told.

rick merritt
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Re: SOI users at 20nm?
rick merritt   4/9/2014 10:32:39 AM
@Austin Tech Watcher: Thanks for the good perspective, David!

rick merritt
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Re: SOI users at 20nm?
rick merritt   4/9/2014 10:35:05 AM
@SOI Lady: I am assuming you mean GloFo which said in the past it would support the process.

No doubt there is some busienss being a second source for ST...but as Austin Tech Watcher noted, there seems to be a diminishing set of supporters.

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Bulk Si, FDSOI and FinFETs
michigan0   4/9/2014 9:19:35 PM

Sang kim


Here are some of the important facts on differences of Bulk Si,  

FDSOI and FinFETs. 


Bulk Si successfully ran several technology nodes such as 95, 

65, 45, 35 but ends at 28nm. In order to suppress transistor 

leakage current or drain/source punchthrough a combination 

of channel doping and retrograde channel implant just below 

the Si surface were used for Bulk Si. However, such a 

combination of the channel doping and retrograde implant 

has a limit as the channel or gate length, Lg decreases to 

20nm because precise control of shallower retrograde channel

implant just below the Si surface becomes increasingly more

difficult, complex and not so effective any more in 

manufacturing, resulting in high device variabilities or 

instabilities in transistor electrical transfer characteristics due 

to high transistor leakage current due to poor process control 

and manufacturability. That is why Intel adopted 22nm 



FDSOI is not the cost issue but transistor device physics 

issue.  FDSOI has two most critical issues: its scalerbility and 

manufacturability. IBM invented FDSOI technology over a 

decade ago and created International SOI consortium to 

develop and manufacture FDSOI but not manufacturable 

today at any technology node yet. IBM exited FDSOI a long 



FDSOI has such a very simple structure consisted of high K

metal gate, thin SOI and thick oxide substrate that often 

make unware of the real issues with FDSOI. The 28nm 

Bulk is in mass production for several years by major 

semiconductor companies such as Intel, TSMC, Samsung 

and others but 28nm FDSOI is not manufacturable today. 

Even if manufactured today, it would not be 

competitive with 28nm Bulk because SOI wafe rcost is 

very much higher than bulk Si wafer. 


FDSOI is not scaleable. The beauty of FinFETS over FDSOI 

is its scaleability. The thin SOI is the key component of 

FDSOI to suppress transistor leakage current or short 

channel effects. In order to suppress transistor leakage 

current for 20nm FDSOI a 5nm thin SOI is required while 

for 20nm FinFETs the Finwidth at the bottom of Fin that is 

equivalent to SOI thickness for FDSOI requires 20nm. 

What a large difference! 20nm for FinFETs vs 5nm for 

FDSOI for suppressing transistor leakage current or short 

channel effects. That is why Intel's FinFETs are scaleable 

to the end of the roadmap, but not FDSOI, not even 14nm 

FDSOI that requires 3.5nm SOI that is close to the 

ultimate quantum confinement limit(3nm). That is why 

Intel 14nm FinFETs will be high volume manufactured in 

2015 at the same time when TSMC 16nm FinFETs volume 

manufacturing starts. Major Semiconductor companies 

will adopt the FinFETs, not FDSOI.

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Re: Bulk Si, FDSOI and FinFETs
AKH0   4/10/2014 10:53:07 AM
I am not sure where you get the 3.5nm thickness from. Although it is a great improvement over 6nm vs 12nm argument you were making not long ago. As publicly stated multiple times and will be shown at VLSI symp in a few months, 14nm FDSOI is using 6nm channel thickness. It uses Si channel for NFET and SiGe for PFET. NONE of the FinFET devices published so far have a strain knob for PFET despite all the performance claim and continue to normalize the current per footprint which I consider cheating as a device engineer - this is exactly how TSMC claimed performance parity or even advantage over Intel 22nm. And by the way there is no 16nm or 14nm gate length in 16nm FinFET technology. The shortest gate length in FinFET is 30nm and low leakage devices go all the way to 50nm. Please see TSMC's paper. Those rule of thumb thickness versus gate length don't come into play when you design technology relevant devices. And believe me I did this for both FinFET and FDSOI for more than 6 years.

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