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20nm Dilemma Explained

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michigan0
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Re: Bulk Si, FDSOI and FinFETs
michigan0   4/19/2014 4:04:10 PM
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Sang Kim

 

The 3.5nm SOI thickness for14nm FDSOI is estimated from 

simulation data published by Professor J. G. Fossum, 

university of Florida in his book "Fundamentals of Ultra-thin

body MOSFETs and FinFETs". See Fig. 3.8 on FD/SOI 

MOSFET with thick BOX.

 

In my opinion even with 6nm SOI thickness for 14nm 

FDSOI the 6nm SOI is too thin to incorporate SIGe for PFET 

in order to be effective. FinFET dose not require a strain 

knob for PFET as well as NFET. Fin-Width has a trepizoidal 

shape that means the Fin-Width decreases with Fin-Hight. 

As a result, most of the high I-on current comes from the 

upper narrow portion of the Fin because the narrow region 

is fully inverted just like double gate transistor. For double 

gate transistor the hightest transistor on-current occurs 

when both top and bottom transistors become inverted.

 

According to just published 2014 VLSI abstracts the 14nm 

FDSOI with forward back bias(FBB) is not manufacturable 

yet, just demonstration. I doubt it is manufactured.

 

I repeat FDSOI has not been volume manufactured at any 

technology yet, and will not be. Major semiconductor 

companies will adopt FinFETs, not FDSOI.  




AKH0
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Re: Bulk Si, FDSOI and FinFETs
AKH0   4/19/2014 4:20:29 PM
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Dear Sang Kim. You are making the assumption that 14nm technology needs a 14nm gate length, which is not true. This is know across all companies. The technology node number is just a label, without any direct connection to any dimension on the device. I agree embedded SiGe is not doable on FDSOI, and that's why I used SiGe in the channel, with performance competing with anything that is out there. However, I do not agree FinFET does not need a strain knob. It does and as far as I have seen (experimentally and by analyzing data from Intel and TSMC so far) eSiGe does NOT work the way it used to. The explanation you provided as only the top of the channel conducting the current actually makes things worse. You are paying the capacitance penalty for the entire gated portion of the fin, so if only the top portion really conducts it's less current for a given capacitance.

michigan0
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Re: Bulk Si, FDSOI and FinFETs
michigan0   4/20/2014 12:40:45 AM
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Sang Kim

 

You disagree that 14nm technology means a 14nm gate or

channel length for 14nm FinFFETs. You said that is not true,

known across all companies. "The technology node number

is just a label.......... ." I can't disagree more. When Intel

and TSMC announced 14nm and 16nm FinFETs respectively

for high volume manufacturing in 2015, they meant 14nm

and 16nm channel or gate length, Lg. 2014 VLSI symposium

featuring a 10nm FinFET platform means a 10nm channel or

gate length, Lg. Otherwise, we can't talk about transistor

leakage current or short channel effects that are the

determining factors for FinFET scailerbility.

 

You miss quoted me here. I didn't say "only the top of the

channel....." I said most of the high I-on current comes from

the upper narrow portion of FinW(width) because the narrow 

region is fully inverted....etc." An important thing to 

remember here is that not the entire FinW area is inverted. 

Because of a trapezoidal nature of Fin shape, FinW at the

bottom is much wider. Therefore, the FinW at bottom is not 

inverted, instead depleted. That is why the high I-on current 

comes from the upper narrow inverted FinW region. FinFET 

doesn't require an additional strain knob that may impact 

adversely the un-doped inverted Fin region. That is why

Intel's 22nm and 14nm FinFETs in volume manufactured 

today don't use additional strain. The maximum high I-on 

current for Intel 14nm FinFET is achieved by maximizing 

the un-doped upper fully inverted FinW region and 

minimizing the fully depleted FinW region at bottom. 

 

   





AKH0
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Re: Bulk Si, FDSOI and FinFETs
AKH0   4/20/2014 10:03:17 AM
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TSMC's 16nm technology has a gate length of 30nm or more. Same is Intel's 22nm. The cross sections have been clearly shown in conferences. 10nm platform that you quote also has a gate length of more than 20 nm as will be shown in June. This is the first time I hear FinFET does not need strain and strain is bad. Please talk to people that run wafers. Whether it's most of the current in the top or all of it, at the end of the day what matters is current per capacitance or gm divided by capacitance. If you do that math FinFET comes shy. Please see broadcom's invited paper at iedm 2013. FinFET ft - even intrinsic , which is simply 1/2pi gm/Cgs comes worse than 20nm planar. We can talk all day how beautiful a PowerPoint FinFET is. But the fact is that one by one people are seeing its problems.

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