Although double patterning is certainly a signficant barrier, a more aggressive shrinking (<0.7x) could bring back some more returns. Actually, the greater concern for me is the self-heating that could be aggravated in these thin silicon devices (FDSOI and FinFET). It's harder for heat to move away from hot spots in thin silicon. Even in the Intel trigate case, it has to move down from the narrowest point (the apex).
Yes, the industry has moved to Finfets to solve the problems with bulk. It's going to be difficult for FDSOI to become mainstream now. A few points:
(1) Yes, Finfets when executed properly give significantly lower wafer costs than FDSOI. That's what I heard from both Intel and TSMC people who made the decision in their respective companies.
(2) SOITEC is known to have significant yield problems getting 5nm or 8nm thin SOI uniformly across the wafer. I heard some bad yield numbers from their employees. The $500 wafer cost assumption is optimistic.
(3) With AMD moving away from SOI and the industry choosing Finfets over FDSOI, SOITEC is in trouble. It's been funding various marketing pushes by hiring consultants and third parties who push SOI... They also fund the SOI consortium. Some of the recent stuff about SOI in the press comes from those efforts. If you speak with decision makers in companies, they say Finfets WHEN EXECUTED WELL, are better, cheaper and more scalable.
(4) SOITEC was formed to commercialize the French Govt's (CEA/LETI's) SOI invention. So, ST Micro, which gets a lot of funding from the French govt, is pushing the technology.
The same situation of 2002/2003, when AMD chose the SOI process for ClawHammer. The problems were numerous, but this decision revealed itself good for AMD, if we see at the recent past. http://www.geek.com/chips/amd-paid-ibm-46-million-to-solve-some-soi-problems-552954/
Today AMD has to do a gamble, and FD-SOI could be a good pick (like Altera and Intel alliance).
I think no one has disagreed that 28 nm bulk planar is the cheap(est) starting point. Going to FDSOI or FinFET adds cost, and going to 20 nm adds cost. With the added cost of FDSOI or FinFET, the shrink should be beyond 20 nm to make up, but is 14 nm even enough? Especially with increased lithography costs at 14 nm only adding to the costs?