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resistion
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Self-heating
resistion   4/4/2014 9:46:42 PM
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Although double patterning is certainly a signficant barrier, a more aggressive shrinking (<0.7x) could bring back some more returns. Actually, the greater concern for me is the self-heating that could be aggravated in these thin silicon devices (FDSOI and FinFET). It's harder for heat to move away from hot spots in thin silicon. Even in the Intel trigate case, it has to move down from the narrowest point (the apex).

Gondalf
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STM micro bias
Gondalf   4/5/2014 3:59:50 PM
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Estimated....estimated....estimated.

Nobody knows the real wafer cost at TSMC or Intel on 22/20nm , not even STM.

Moreover STM has yet to give hard numbers about superiority of FD SOI versus FinFet in high power, medium power, low power, very low power transistors.

STM is obscure....smoky. What about the comparison between FD SOI and Bulk??? why not between FD SOI and Bulk + FinFet ??? strange thing indeed !!

All the industry is going to FinFet, following Intel that has a three years lead and experience over all contenders in high volume shipment of FinFet devices.

I assume that Intel has chosen FinFet over SOI because it gives the better performance, the lower power consumption and the lower per wafer cost at 22/14/10nm nodes.

No matter what is saying STM, all the foundries have done definitively their choice.......FinFet. The history is written right now.

Fottemberg
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FD-SOI and AMD
Fottemberg   4/5/2014 5:13:56 PM
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Will AMD produce CPUs or GPUs on FD-SOI during 2014?

Gondalf
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Re: FD-SOI and AMD
Gondalf   4/5/2014 6:11:25 PM
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No Amd has shifted to bulk definitively.

The STM micro bias has omitted the necessity of dual patterning at 20nm FD SOI, double patterning and some quadruple at 14nm FD SOI etc....

The interconnection thikness is not related with the type of transistor and with exotic substrates. 

The real cost is in interconnection and most of the costs of research are devoted to its improvement at the finest nodes.  

3D Guy
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Finfets the industry's solution to the problem
3D Guy   4/6/2014 12:53:23 AM
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Yes, the industry has moved to Finfets to solve the problems with bulk. It's going to be difficult for FDSOI to become mainstream now. A few points: (1) Yes, Finfets when executed properly give significantly lower wafer costs than FDSOI. That's what I heard from both Intel and TSMC people who made the decision in their respective companies. (2) SOITEC is known to have significant yield problems getting 5nm or 8nm thin SOI uniformly across the wafer. I heard some bad yield numbers from their employees. The $500 wafer cost assumption is optimistic. (3) With AMD moving away from SOI and the industry choosing Finfets over FDSOI, SOITEC is in trouble. It's been funding various marketing pushes by hiring consultants and third parties who push SOI... They also fund the SOI consortium. Some of the recent stuff about SOI in the press comes from those efforts. If you speak with decision makers in companies, they say Finfets WHEN EXECUTED WELL, are better, cheaper and more scalable. (4) SOITEC was formed to commercialize the French Govt's (CEA/LETI's) SOI invention. So, ST Micro, which gets a lot of funding from the French govt, is pushing the technology.

Fottemberg
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Like 2003
Fottemberg   4/6/2014 8:39:04 AM
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The same situation of 2002/2003, when AMD chose the SOI process for ClawHammer. The problems were numerous, but this decision revealed itself good for AMD, if we see at the recent past. http://www.geek.com/chips/amd-paid-ibm-46-million-to-solve-some-soi-problems-552954/


Today AMD has to do a gamble, and FD-SOI could be a good pick (like Altera and Intel alliance).





HangLai
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The author is exaggerate his knowledge.
HangLai   4/6/2014 9:26:39 AM
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The author is exaggerate his knowledge.  The industrial is not moving into SOI for some time to come.

resistion
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Talking around the actual point
resistion   4/6/2014 9:45:56 AM
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I think no one has disagreed that 28 nm bulk planar is the cheap(est) starting point. Going to FDSOI or FinFET adds cost, and going to 20 nm adds cost. With the added cost of FDSOI or FinFET, the shrink should be beyond 20 nm to make up, but is 14 nm even enough? Especially with increased lithography costs at 14 nm only adding to the costs?

resistion
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CEO
FDSOI wafer cost compensation?
resistion   4/6/2014 10:12:26 AM
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Clearly the big cost issue for FDSOI is the special wafer preparation with only some nm thin Si. On the other hand, it has been claimed FDSOI is implant-free so there is some cost reduction there.

As said earlier, the deal breaker is self-heating.

HJ88
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Additional Inputs
HJ88   4/7/2014 11:48:13 AM
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1. Have detailed data on wafer cost and die cost which support projections shown. The cost data shown was not provided by STM, but independently developed by IBS.

2. FinFETs will ramp into high volume production. The questions are:
  • When?
  • How much of the market will FinFETs take in the time frame through 2017?

The area of concern is for mobile platforms because of the cost challenges.

3. Qualcomm 810 and 808 are very impressive products, and the target for initial devices is H1/2015. Will tie into Mobile World Congress (Barcelona).

Is it realistic to expect the next-generation products in FinFETs in H1/2016, or is H1/2017 a more realistic projection?

Qualcomm is the volume leader from a foundry perspective along with potentially Apple.

4. Are there other options that are more cost-effective?

Fully agree that without a strong supply chain, FD SOI will not become widely adopted. Key question is whether there will be support outside of STM. Any ideas?

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