A new study comparing the Intel X86, the ARM and MIPS CPUs finds that microarchitecture is more important than instruction set architecture, RISC or CISC.
If you are one of the few hardware or software developers out there who still think that instruction set architectures, reduced (RISC) or complex (CISC), have any significant effect on the power, energy or performance of your processor-based designs, forget it.
Ain't true. What is more important is the processor microarchitecture — the way those instructions are hardwired into the processor and what has been added to help them achieve a specific goal.
This is the over-arching conclusion of a study recently published in the ACM Transactions on Computer Systems. In the paper, "ISA Wars: Understanding the Relevance of ISA being CISC or RISC," authors Emily Blem, Jakrishnan Menon, Thiruvengadam Vijayaraghavan, and Karthhikeyan Sankaralingam, report the results of a study over the last four years or so by the University of Wisconsin (Maidison) Vertical Research Group(VRG).
Platforms used in RISC vs CISC ISA study
Vijayaraghavan, Associate Professor, Computer Sciences, Electrical and Computer Engineering at UMM, said the study is the most comprehensive analysis to date on all aspects of the design and implementation of three major architectures: Intel's x86, the ARM architecture, and Imagination Technology's MIPS CPU.
"While there may have been differences in the past between RISC and CISC ISAs in current architectures, there certainly aren't now in terms of the parameters we focused on: performance, power, and energy,” Sankaralingam told EE Times. “Where the ISA is lacking, the microarchitecture is enhanced to make up for it, and vice versa."
He said that that there is only one true RISC architecture out there, Imagination's MIPS, which is based on the architecture developed by researchers from Stanford University. The X86 was originally a pure CISC design, but over the years has taken on a much more RISC-like structure while ARM's approximately RISC architecture has taken on more CISC features, including the addition of the Thumb 1 and Thumb 2 ISAs.
Findings of VRG RISC vs CISC study
(Source: University of Minnesota)
"So basically what it comes down to is comparing today's implementations of the processors from Intel, ARM, and Imagination in today's market environment. And by almost every measure we used, even there ISA is irrelevant."
Because previous studies were handicapped by comparisons between systems with varying hardware and software resources, Sankaralingam said the VRG team worked hard to make sure measurements were made on roughly equivalent platforms and in roughly comparable environments. To separate out implementation and ISA effects, where possible they used multiple chips for each ISA with similar microarchitectures.
This study confined its comparisons to those implementations of the Cortex-A8 or higher, with little focus on any of the Cortex-M devices. "The reason for this is simple: one of our goals was to have platforms we could compare and quantify," he said. "There is no way to do that below the A9, in terms of competitive architectures." In the Cortex-M0 environment, where ARM is competing with 8-bit MCUs over the 1-20 MHz and 2-50 mWatts range, the operating overheads of the X86 instruction set makes that untenable.
The team's evaluations were performed on one MIPS implementation (Loongson), three ARM platforms (Cortex- A8, Cortex-A9, and Cortex-A15), and three x86-based designs (Atom, Bobcat, and Sandybridge i7). They also used the same operating system, Linux 2.6 LTS (but 2.8 on the A5) and the same gss 4.4-based cross compiler front end. For mobile client workloads, they used the CoreMark and Webkit benchmarks. For desktop apps, SPECCPU2006 was used, while server benchmark workloads used included lightpd and CLucerne.
The implementations span diverse ISAs and within each ISA, diverse microarchitectures. "Overall, our choice of platforms provides a reasonably equal footing, and we performed detailed analysis to isolate out microarchitecture and technology effects, "said Sankaralingam. The VRG team did performance comparisons of the processors in terms of execution time, cycle count, instruction count, instruction format and mix, microarchitecture and ISA influence on microarchitecture. Power and energy analysis measurements were also extensive: average power, average technology independent power, and average energy, among others.
According to Sankaralingam, the takeaway on this report is that although ISA is relevant to power and performance by virtue of support for various specializations (virtualization, accelerators, floating point arithmetic, etc.), whether the ISA is RISC or CISC is largely irrelevant for today’s mature microprocessor design world.
"Based on this study, developers can safely consider ARM, MIPS, and x86 processors simply as engineering design points optimized for different levels of performance," he said. “There's nothing fundamentally more energy-efficient in one ISA class versus another."
In the concluding paragraph of the report, the authors write: "It appears that decades of hardware and compiler research has enabled efficient handling of both RISC and CISC ISAs, and both are equally positioned for the coming years of energy-constrained innovation."
While Sankaralingam thinks the VRG team developed an exhaustive and rigorous methodology for its study he said “there are many ways to analyze the data.” So for those interested in doing their own analysis, the raw data for the study can be downloaded from the University of Wisconsin VTG web page.
You can also download “ISA Wars: Understanding the Relevance of ISA being CISC or RISC” at the Association of Computing Machinery web site. Even if you are not a member of the Association of Computing Machinery, and so have to pay a $15 fee to download the paper, it is worth the one-time price.
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