Breaking News
Winbond at a Crossroads
9/10/2013

Image 1 of 3      Next >

Krishna Shekar, director of strategic marketing at Winbond.
Krishna Shekar, director of strategic marketing at Winbond.

Image 1 of 3      Next >

Return to Article

View Comments: Threaded | Newest First | Oldest First
rick merritt
User Rank
Author
Winbond
rick merritt   9/10/2013 9:21:09 AM
NO RATINGS
Boy, there's a name I haven't heard in awhile!

resistion
User Rank
Author
NAND 's burden
resistion   9/12/2013 6:56:18 AM
NO RATINGS
A lot of ECC, probably.

Peter Clarke
User Rank
Author
Re: NAND 's burden
Peter Clarke   9/13/2013 5:58:51 AM
NO RATINGS
Yes 

Clearly at the leading edge, MLC NAND flash requires extensive ECC and also a controller that will keep moving data on so that all the memory cells get similar wear....as they can only do a limited number of read/write cycles and ECC to correct for altered bits adds to the wear.

One implication of this "wear leveling" is that at the extreme the effective capacity of a leading-edge NAND flash memory reduces over time.

I am not sure whether the manufacturers provide additional capacity so that the memory "wears down" toward the advertized capacity ...or they produce what they produce and reckon it is down to the controller to "manage" the situation.

resistion
User Rank
Author
Re: NAND 's burden
resistion   11/20/2013 8:13:25 PM
NO RATINGS
The controller is a large hidden cost for NAND flash. Anyone figured this out yet?

Most Recent Comments
michigan0
 
SteveHarris0
 
realjjj
 
SteveHarris0
 
SteveHarris0
 
VicVat
 
Les_Slater
 
SSDWEM
 
witeken
Most Recent Messages
9/25/2016
4:48:30 PM
michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed