I think CeRAM array fabrication and evaluation is the next step as indicated below. However, if you are suggesting that in a general sense there is some fundamental limit to array size related to read current, or read current density, or you have some formula that links and limits those variables then please share it with us.
For any of the emerging memory technologies looking to achieve large array bit densities, mimnimizing power requires finding the lowest possible write,erase,read current. In many cases the solution will be in array architecture, layout and sense amplifier design.
hello, maybe I miss something but the current densities are very low from the I/V curves shown by the writer, how do you expect to have fast random access times froma memory array with such low currents? thanks
Right on. It is not an easy task to discriminate what is the dominant phase transition mechanism in the reative region of where the filament is. The Schottky barrier is a space charge region which is not ever a constant potential area - in fact it goes from a high field to the zero field point wher the space charge is fully compensated by the bulk charge, In fact all semiconductor devices dependend on pn,Schottky and MOs space charge regions - all call this the 5 Schikley equations and 3 regions devices. The field distribution and the cyrstal field plus defects are a deadly mix for a stable memory device. And, since there is no hysterectic behavior intrnisic to semiconductors, we have to live with oxides and the like to make nonvolatile memories (where hysteresis is a must). Now in FLASH you have charge trapping in the floating gate causing threshold voltage hysteresis. We know that that is not a great solution in terms of endurance and power. Now, shemes as you describe that technically end up in charge trapping are not of potentially great future either, as eventually reliability lomits in controlling the traps squeeze you in. So, when we saw the universality of CeRAM being a quantum phenomenon that is not dependent in single crystals and right off the bat it shows easy integration and fulfills a cost/performance market node, you can imagine our excitement. But to tell you the truth, the academic side of me, specially in device physics, is what really turn me on.
Yes, I agree a filamentary forming-free device is still filamentary. Recently, there have been pictures of filamentary structures (mostly TaOx-based) and unexpectedly there wasn't a single dominant one, but it looked like many at the interface. Sometimes it is reported the filament is like a metal, sometimes like a semiconductor. I sometimes wonder if the filament is going through the metal-insulator transition. And with many filaments occurring, where to draw the line separating from area-based...even Schottky and STT can be non-uniform.
There have been many examples of forming-free resistive memories. In the ideal case, the RESET state is virtually the same as the initial. But I haven't surveyed this extensively in a while, so I can't comment how common this is.
I think that you meant Vset, as in these cases, the forming voltage is of the same order as the set voltage. These arguments of "No forming needed" have entered the arena recently, specially in HfO. But, they do not mean that no filaments are made. And, again, it is a matter of reliability. How reliable is the "disconnect" region of these filaments. Can one really bank on random electrochemical reactions for a memory. Some will say that certain tailoring of the filament map etc. can eventually make a good memory device. I heard a lot about this kind of argument when we were in the Phase Change Memory area. I do not believe that strucutral thermally driven phase transitions are an answer to 10 nm devices and beyond. We have to have something better - something truly quantum and not metallurgical.
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