Signal Processing DesignLine Blog
Startup Align technologies today revealed a technology that promises to greatly reduce the cost and complexity of SerDes solutions. The company's technology centers around its patented Align Lock Loop (ALL) synchronization technique. Standard SerDes implementations require expensive clock data recovery (CDR) and circuitry and PLLs to synchronize the data stream. ALL eliminates this circuitry from the master device. (The slave device retains some of this circuitry.) As a bonus, ALL makes it appear that all SerDes devices in the system are in the same clock domain.
The ALL technology has great potential for systems that need to connect to high-speed ADCs, and for systems that require high-speed inter-processor and inter-board communication. It's worth keeping an eye on this technology.