The multicore wave is breaking. From Intel's two, four, and eight core offerings, to multicore DSPs from the likes of TI and Freescale, to massively parallel processor startups going for ultra high performance, DSP engineers have no shortage of multicore options. These architectures take many diverging approaches and present different challenges, but they all share a common problem: providing efficient inter-processor communication (IPC) while avoiding race conditions, deadlocks, and other fatalities.
For architectures with relatively few cores such as Intel's, IPC is typically handled by the OS. For a good overview of OS approaches to multicore check out this how-to by QNX systems.
Massively parallel processors, which often consist of dozens or even hundreds of cores, have taken a different approach. Because individual processors are small and usually specialized to some extent, running an OS on each would be inefficient if not impossible. Instead, companies have devised novel IPC schemes tailored to their architecture and target applications. PicoChip, for instance, makes chips with roughly 300 cores and has focused narrowly wireless basestations. In their architecture processors communicate via a TDM scheme where all communications are determined at compile time. This makes sense, because the simple cores in the PicoChip architecture doesn't need complex, flexible IPC—they just need reliable connections for their repetitive tasks.
Several IP companies are also offering novel IPC approaches. For example, Tensilica's provides ports that allow cores to communicate directly, rather than through shared memory (as is usually the case). As another example, startup 3Plus1 has a data-flow driven scheme that synchronizes cores automatically.
It remains to be seen which of these diverging approaches will win, but how multicores solve the IPC problem will likely be a key differentiator.