ESL promises big productivity gains. IP re-use is the key to making that dream come true.
In the last few years there has been a lot of buzz around Electronic System Level (ESL) design methodologies. These methodologies model an entire embedded system using a high-level language such as C, MATLAB, or SystemC. These models are used to explore architectural tradeoffs and ensure a correct design before development work begins. The models can even be used to generate an initial implementation of the design.
The need for ESL (or as The MathWorks calls it, Model Based Design) is obvious. Hardware and software architecture are getting mind-bendingly complicated, with technologies like multiprocessors and FPGAs becoming commonplace. To deal with this rising complexity, designers need a corresponding improvement in productivity—and ESL promises to deliver a big productivity boost.
Knowing how important ESL has become, I was intrigued by CoWare's ESL 2.0 announcement. Aside from the usual capabilities you'd expect from ESL tools (virtual hardware modeling, a graphical programming environment, and extensive IP), I was pleasantly surprised by two of the new capabilities in the "2.0" release: the ability to pull existing RTL and MATLAB code into CoWare's SystemC modeling environment. Both capabilities address what had been a gaping hole in the ESL value proposition: IP reuse. Chip design companies have mountains of legacy RTL and MATLAB code. For ESL tools to deliver the productivity gains they promise, they need to leverage these legacy designs.