Structured ASIC company eASIC now offers Tensilica cores free of charge. If you have a medium-volume app, you should check this out.
A recent announcement got me thinking about structured ASICs, a technology that (in my quasi-humble opinion) hasn't gotten the attention it deserves. On November 26th, structured ASIC maker eASIC announced it was offering Tensilica's Diamond processor cores free of charge—no upfront fees, no royalties. eASIC customers pay only for Tensilica's tools, which run a reasonable $1k a seat.
This deal is obviously good for eASIC, but it also makes a lot of sense for Tensilica. If you believe Tensilica's numbers, its cores offer superior performance, area, and power. However, the company has to pry customers away from industry behemoths ARM and MIPS. These market leaders have entrenched customer relationships, mature tools, and abundant IP. The deal with eASIC gives companies a strong incentive to make the switch.
Structured ASICs are a particularly good opening for Tensilica because they're typically used for medium-volume designs (see below for an explanation). Medium-volume designs often come from medium-size companies, and these are precisely the companies where Tensilica has the hardest sell. Large companies typically have many different designs, and therefore have a broad selection of licenses. Adding Tensilica to the mix is a minor deal for these large companies. Smaller companies, on the other hand, can only afford a small number of licenses, so it is harder for Tensilica to get in the door. The deal with eASIC makes it much easier for these companies to start using Tensilica's cores.
A little background on structured ASICs: Like FPGAs, structured ASICs implement custom logic by connecting fixed, low-level logic elements in pre-fabricated metal layers. They offer ASIC-like performance and power with FPGA-like design costs. They achieve this by being less flexible than ASICs or FPGAs. For instance, clocks, test structures, and application specific IP blocks are often pre-defined in structured ASICs.
Structured ASICs are best for medium-volume designs. FPGAs have have lower up-fronts costs and are usually a better choice for low-volume apps. ASICs have significantly lower per-unit costs and are therefore a better fit for high-volume apps. For a discussion of where structured ASICs are succeeding (and where they aren't), check out this well written article, 'Where Do Structured ASICs Fit'.