Trouble with timing constraints is an annoyance that plagues many a design engineer, but the results of a recent survey suggest that the issue can cause more than a few headaches and some lost hours of sleep.
Less than 10 percent of respondents to the survey—which was conducted by EDA vendor Atrenta Inc.— indicated that timing constraints rarely presented a problem in the design flow. More than 10 percent said timing constraints created a problem every day, 29 percent said they created problems a few times in a typical project and nearly 52 percent said they created problems frequently in a typical project.
More troubling, 29 percent of respondents said that in cases were timing constraints presented a problem the consequences included silicon failure. Nearly 59 percent said consequences included tape out delay. In all, nearly 85 percent of respondents said timing constraints issues resulted in difficulties meeting timing.
What are designers doing in the face of such a vexing issue that could potentially cause their chip to fail? Most—nearly 73 percent—responded that they implemented stricter guidelines for timing constraint development. Nearly 14 percent of respondents said they had made no changes to their design flow or process to combat timing constraint issues.
"In effect, 73 percent of respondents said, 'We'll just try harder,' " said Ron Craig, senior marketing manager at Atrenta. "Too many heads are still stuck in the proverbial sand. People don't fully recognize the magnitude of the problem."
Half of the respondents said they verify timing constraints manually. Sixty-eight percent said they rely on synthesis and timing tools to point out the mistakes. (Obviously, respondents were allowed to give more than one answer to the question.
But according to Craig, synthesis and timing tools are not really designed to catch bad constraints. They end up missing a lot of things, such as overlapping constraints, he said. Manual verification has become too difficult as designs have grown exponentially, he added.
"The solution is to be more proactive," Craig said. "You can have 95 percent good constraints before you even start using them. If you know up front that things are good then you avoid all of these issues and things sneaking through."
You knew this was coming. Surprise: Atrenta sells a tool, SpyGlass Constraints, which automates the creation, validation and management of constraints. The survey—a survey of Atrenta customers which 66 people responded too—found that only about 26 percent of respondents were using SpyGlass Constraints. Eighteen percent of respondents said they were using another third-party tool to verify and manage timing constraints.
Obviously, Craig believes more designers to need to adopt third-party tools to manage constraints. And it's a safe bet he prefers that they use SpyGlass Constraints. But he acknowledged that it can be a tough sell to get customers to pony up to add a new tool to their flow. A certain part of that, he said, is human nature—designers feel that if they overcome the timing constraints difficulties with their last chip they can do it again with their next without spending money for a new tool.
Craig's message to designers: "Your experience and your productivity isn't keeping up with the complexity of your constraints and the number of issues you are taking on."
The sad part is a lot of people have timing problems, they just don't recognize them.
Any time you have spurious or intermittant problems, they are most likely caused by timing issues. I have tried to get people to do a timing analysis of each thread at the system level, but most just say its not a problem and go on.
Timing errors can waste a tremendous number of testing hours, plus they really make users angry when the software behaves erratically.
Software is more than just an App! It represents a controlled method for executing a process within a system environment. The environment can be a smart phone, washing machine, scientific satellite, car, or any of the billion of computer controlled devices now in use world wide. Timing is every bit as important as chosing the right processor, bus speed, storage or any of the other system components. If the timing does not work, one or all of the other components become useless.
In short, if you do not conduct a timing analysis, then you have a potential vulnerability in your system. If you care at all about the quality of the work you do, then you need to make sure that your application works under all types of conditions and has a prepared method to deal with the system degridation brought on by timing issues.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.