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Dispelling the myth about analog scaling

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old account Frank Eory
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re: Dispelling the myth about analog scaling
old account Frank Eory   2/22/2012 9:44:24 PM
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Analog does scale, but not to the same degree as digital -- and some analog circuits scale better than others. This isn't really a new revelation, although the issues of voltage headroom and matching are no doubt worse at 32 or 22 nm than they were back at 130 or 90 nm.

elPresidente
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re: Dispelling the myth about analog scaling
elPresidente   2/23/2012 4:23:50 AM
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Analog does scale. But nobody so far has mentioned that its performance starts to really suck. That's what Shor slyly refers to as "just need to do some optimization". Painting analog with a broad brush from a temperature sensor implementation in a microprocessor, using a 'digital" process is a joke. Intel speaking against TI? Come on, EE Times - who's the analog expert among those two and who is the RTL jockey in terms of credibility? Are there any engineers in da house? All I hear is bleating.

truekop
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re: Dispelling the myth about analog scaling
truekop   2/23/2012 4:51:53 AM
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I guess dylan needs to get some counseling on what high performance analog design is ....companies like linear tech and ADI wouldnt exist if amplifier/converter design could be done at 32nm...

kdboyce
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re: Dispelling the myth about analog scaling
kdboyce   2/23/2012 6:52:14 AM
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Also, try scaling the SNR and delivered power to the load. It ain't that easy.

rf_austin
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re: Dispelling the myth about analog scaling
rf_austin   2/29/2012 3:06:43 PM
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The message in this article would be much more believable if a complex analog circuit were presented. When Intel gets to the point that it is combining power amplifiers, analog signal conditioning, and frequency synthesizers in a single chip at 22nm, I will stand up and take notice. Until then, this reads like me adding a flip flop to one of my circuits and declaring I'm a digital designer.

Rachael
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re: Dispelling the myth about analog scaling
Rachael   10/3/2012 4:56:20 AM
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This is the kind of debate where people argue about semantics. What do you mean by area scaling? Do you mean, "an analog circuit's performance scales similarly to a digital circuit on a logic process with a 0.5x reduction in active device area?" if so, it has been known for a long time that headroom collapse, device noise, variation, and increase in spec (such as VCO gain increase) make this impossible. Analog on advanced logic processes (which Mr Shor's application concerns) has dwelled in a "relaxed" scaling zone where elimination of margin and over-design, and statistical design techniques allow approximately a 0.7 to 0.8x scaling per generation. This is not sustainable and we are already seeing the need to increase power for iso-performance. Now, if you mean, "can an analog system's area be reduced by 50% per generation through optimization, digital assisted design, circuit innovation, etc", the as we have seen the answer is yes for now. We will see big reductions as designs move to the digital domain. I have had the pleasure of designing analog circuits on Intel's lead technology for almost 20 years, but I do not speak for Intel in this forum.

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